interrupts.cc (5254:c555f8b07345) interrupts.cc (5646:0a488a147fb8)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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151 {
152 MiscReg compare = tc->readMiscRegNoEffect(MipsISA::Compare);
153 MiscReg count = tc->readMiscRegNoEffect(MipsISA::Count);
154 if (compare == count)
155 return true;
156 return false;
157 }
158
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 142 unchanged lines hidden (view full) ---

151 {
152 MiscReg compare = tc->readMiscRegNoEffect(MipsISA::Compare);
153 MiscReg count = tc->readMiscRegNoEffect(MipsISA::Count);
154 if (compare == count)
155 return true;
156 return false;
157 }
158
159
160 uint64_t Interrupts::get_vec(int int_num)
161 {
162 panic("MipsISA::Interrupts::get_vec() is not implemented. \n");
163 M5_DUMMY_RETURN
164 }
165*/
166void Interrupts::post(int int_num, ThreadContext* tc)
167{
168 DPRINTF(Interrupt, "Interrupt %d posted\n", int_num);
169 if (int_num < 0 || int_num >= NumInterruptLevels)
170 panic("int_num out of bounds\n");
171
172 uint8_t intstatus= getCauseIP_(tc);

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247 return false;
248}
249void Interrupts::updateIntrInfo(ThreadContext *tc) const
250{
251 //Nothing needs to be done.
252 ;
253}
254
159*/
160void Interrupts::post(int int_num, ThreadContext* tc)
161{
162 DPRINTF(Interrupt, "Interrupt %d posted\n", int_num);
163 if (int_num < 0 || int_num >= NumInterruptLevels)
164 panic("int_num out of bounds\n");
165
166 uint8_t intstatus= getCauseIP_(tc);

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241 return false;
242}
243void Interrupts::updateIntrInfo(ThreadContext *tc) const
244{
245 //Nothing needs to be done.
246 ;
247}
248
255uint64_t Interrupts::get_vec(int int_num)
256{
257 panic("MipsISA::Interrupts::get_vec() is not implemented. \n");
258 M5_DUMMY_RETURN
259 }
260
261bool Interrupts::interruptsPending(ThreadContext *tc) const
262{
263 //if there is a on cpu timer interrupt (i.e. Compare == Count)
264 //update CauseIP before proceeding to interrupt
265 if (onCpuTimerInterrupt(tc)){
266 DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc)==true\n");
267 //determine timer interrupt IP #
268 MiscReg intctl = tc->readMiscRegNoEffect(MipsISA::IntCtl);

--- 17 unchanged lines hidden --- 		249bool Interrupts::interruptsPending(ThreadContext *tc) const
250{
251 //if there is a on cpu timer interrupt (i.e. Compare == Count)
252 //update CauseIP before proceeding to interrupt
253 if (onCpuTimerInterrupt(tc)){
254 DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc)==true\n");
255 //determine timer interrupt IP #
256 MiscReg intctl = tc->readMiscRegNoEffect(MipsISA::IntCtl);

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