interrupts.cc (10474:799c8ee4ecba) interrupts.cc (11566:b11410957c9e)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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100
101void
102Interrupts::clearAll()
103{
104 fatal("Must use Thread Context when clearing MIPS Interrupts in M5");
105}
106
107
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 91 unchanged lines hidden (view full) ---

100
101void
102Interrupts::clearAll()
103{
104 fatal("Must use Thread Context when clearing MIPS Interrupts in M5");
105}
106
107
108
109Fault
110Interrupts::getInterrupt(ThreadContext * tc)
108bool
109Interrupts::checkInterrupts(ThreadContext *tc) const
111{
110{
112 DPRINTF(Interrupt, "Interrupts getInterrupt\n");
111 if (!interruptsPending(tc))
112 return false;
113
114 //Check if there are any outstanding interrupts
115 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
116 // Interrupts must be enabled, error level must be 0 or interrupts
117 // inhibited, and exception level must be 0 or interrupts inhibited
118 if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) {
119 // Software interrupts & hardware interrupts are handled in software.
120 // So if any interrupt that isn't masked is detected, jump to interrupt
121 // handler
122 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
113
114 //Check if there are any outstanding interrupts
115 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
116 // Interrupts must be enabled, error level must be 0 or interrupts
117 // inhibited, and exception level must be 0 or interrupts inhibited
118 if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) {
119 // Software interrupts & hardware interrupts are handled in software.
120 // So if any interrupt that isn't masked is detected, jump to interrupt
121 // handler
122 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
123 if (status.im && cause.ip) {
124 DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
125 (unsigned)status.im, (unsigned)cause.ip);
126 return std::make_shared<InterruptFault>();
127 }
123 if (status.im && cause.ip)
124 return true;
125
128 }
129
126 }
127
130 return NoFault;
128 return false;
131}
132
129}
130
131Fault
132Interrupts::getInterrupt(ThreadContext * tc)
133{
134 assert(checkInterrupts(tc));
135
136 StatusReg M5_VAR_USED status = tc->readMiscRegNoEffect(MISCREG_STATUS);
137 CauseReg M5_VAR_USED cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
138 DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
139 (unsigned)status.im, (unsigned)cause.ip);
140
141 return std::make_shared<InterruptFault>();
142}
143
133bool
134Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
135{
136 MiscReg compare = tc->readMiscRegNoEffect(MISCREG_COMPARE);
137 MiscReg count = tc->readMiscRegNoEffect(MISCREG_COUNT);
138 if (compare == count && count != 0)
139 return true;
140 return false;

--- 33 unchanged lines hidden --- 		144bool
145Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
146{
147 MiscReg compare = tc->readMiscRegNoEffect(MISCREG_COMPARE);
148 MiscReg count = tc->readMiscRegNoEffect(MISCREG_COUNT);
149 if (compare == count && count != 0)
150 return true;
151 return false;

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