1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 22 unchanged lines hidden (view full) --- 31 * Korey Sewell 32 */ 33 34#include "arch/mips/interrupts.hh" 35#include "arch/mips/isa_traits.hh" 36#include "arch/mips/pra_constants.hh" 37#include "base/trace.hh" 38#include "cpu/thread_context.hh" |
39#include "debug/Interrupt.hh" |
40 41namespace MipsISA 42{ 43 44static inline uint8_t 45getCauseIP(ThreadContext *tc) { 46 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); 47 return cause.ip; --- 126 unchanged lines hidden --- |