1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 * Kevin Lim
31 * Korey Sewell
32 */
33
34#include "arch/mips/interrupts.hh"
35#include "arch/mips/isa_traits.hh"
36#include "arch/mips/pra_constants.hh"
37#include "base/trace.hh"
38#include "cpu/thread_context.hh"
39
40namespace MipsISA
41{
42
43static inline uint8_t
44getCauseIP(ThreadContext *tc) {
45 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
46 return cause.ip;
47}
48
49static inline void
50setCauseIP(ThreadContext *tc, uint8_t val) {
51 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
52 cause.ip = val;
53 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
54}
55
56void
57Interrupts::post(int int_num, ThreadContext* tc)
58{
59 DPRINTF(Interrupt, "Interrupt %d posted\n", int_num);
60 if (int_num < 0 || int_num >= NumInterruptLevels)
61 panic("int_num out of bounds\n");
62
63 uint8_t intstatus = getCauseIP(tc);
64 intstatus |= 1 << int_num;
65 setCauseIP(tc, intstatus);
66}
67
68void
69Interrupts::post(int int_num, int index)
70{
71 fatal("Must use Thread Context when posting MIPS Interrupts in M5");
72}
73
74void
75Interrupts::clear(int int_num, ThreadContext* tc)
76{
77 DPRINTF(Interrupt, "Interrupt %d cleared\n", int_num);
78 if (int_num < 0 || int_num >= NumInterruptLevels)
79 panic("int_num out of bounds\n");
80
81 uint8_t intstatus = getCauseIP(tc);
82 intstatus &= ~(1 << int_num);
83 setCauseIP(tc, intstatus);
84}
85
86void
87Interrupts::clear(int int_num, int index)
88{
89 fatal("Must use Thread Context when clearing MIPS Interrupts in M5");
90}
91
92void
93Interrupts::clearAll(ThreadContext *tc)
94{
95 DPRINTF(Interrupt, "Interrupts all cleared\n");
96 uint8_t intstatus = 0;
97 setCauseIP(tc, intstatus);
98}
99
100void
101Interrupts::clearAll()
102{
103 fatal("Must use Thread Context when clearing MIPS Interrupts in M5");
104}
105
106
107
108Fault
109Interrupts::getInterrupt(ThreadContext * tc)
110{
111 DPRINTF(Interrupt, "Interrupts getInterrupt\n");
112
113 //Check if there are any outstanding interrupts
114 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
115 // Interrupts must be enabled, error level must be 0 or interrupts
116 // inhibited, and exception level must be 0 or interrupts inhibited
117 if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) {
118 // Software interrupts & hardware interrupts are handled in software.
119 // So if any interrupt that isn't masked is detected, jump to interrupt
120 // handler
121 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
122 if (status.im && cause.ip) {
123 DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
124 (unsigned)status.im, (unsigned)cause.ip);
125 return new InterruptFault;
126 }
127 }
128
129 return NoFault;
130}
131
132bool
133Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
134{
135 MiscReg compare = tc->readMiscRegNoEffect(MISCREG_COMPARE);
136 MiscReg count = tc->readMiscRegNoEffect(MISCREG_COUNT);
137 if (compare == count && count != 0)
138 return true;
139 return false;
140}
141
142void
143Interrupts::updateIntrInfo(ThreadContext *tc) const
144{
145 //Nothing needs to be done.
146}
147
148bool
149Interrupts::interruptsPending(ThreadContext *tc) const
150{
151 //if there is a on cpu timer interrupt (i.e. Compare == Count)
152 //update CauseIP before proceeding to interrupt
153 if (onCpuTimerInterrupt(tc)) {
154 DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");
155 //determine timer interrupt IP #
156 IntCtlReg intCtl = tc->readMiscRegNoEffect(MISCREG_INTCTL);
157 uint8_t intStatus = getCauseIP(tc);
158 intStatus |= 1 << intCtl.ipti;
159 setCauseIP(tc, intStatus);
160 }
161
162 return (getCauseIP(tc) != 0);
163
164}
165
166}
167
168MipsISA::Interrupts *
169MipsInterruptsParams::create()
170{
171 return new MipsISA::Interrupts(this);
172}