faults.hh (8809:bb10807da889) faults.hh (10417:710ee116eb68)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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97 }
98
99 FaultVect
100 vect(ThreadContext *tc) const
101 {
102 return base(tc) + offset(tc);
103 }
104
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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97 }
98
99 FaultVect
100 vect(ThreadContext *tc) const
101 {
102 return base(tc) + offset(tc);
103 }
104
105 void invoke(ThreadContext * tc,
106 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
105 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
106 StaticInst::nullStaticInstPtr);
107};
108
109template <typename T>
110class MipsFault : public MipsFaultBase
111{
112 protected:
113 static FaultVals vals;
114 public:

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129{
130 public:
131 bool isMachineCheckFault() { return true; }
132};
133
134class ResetFault : public MipsFault<ResetFault>
135{
136 public:
107};
108
109template <typename T>
110class MipsFault : public MipsFaultBase
111{
112 protected:
113 static FaultVals vals;
114 public:

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129{
130 public:
131 bool isMachineCheckFault() { return true; }
132};
133
134class ResetFault : public MipsFault<ResetFault>
135{
136 public:
137 void invoke(ThreadContext * tc,
138 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
137 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
138 StaticInst::nullStaticInstPtr);
139
140};
141
142class SoftResetFault : public MipsFault<SoftResetFault>
143{
144 public:
139
140};
141
142class SoftResetFault : public MipsFault<SoftResetFault>
143{
144 public:
145 void invoke(ThreadContext * tc,
146 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
145 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
146 StaticInst::nullStaticInstPtr);
147};
148
149class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
150{
151 public:
147};
148
149class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
150{
151 public:
152 void invoke(ThreadContext * tc,
153 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
152 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
153 StaticInst::nullStaticInstPtr);
154};
155
156class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
157{
158 protected:
159 int coProcID;
160 public:
161 CoprocessorUnusableFault(int _procid) : coProcID(_procid)
162 {}
163
164 void
154};
155
156class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
157{
158 protected:
159 int coProcID;
160 public:
161 CoprocessorUnusableFault(int _procid) : coProcID(_procid)
162 {}
163
164 void
165 invoke(ThreadContext * tc,
166 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
165 invoke(ThreadContext * tc, const StaticInstPtr &inst =
166 StaticInst::nullStaticInstPtr)
167 {
168 MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
169 if (FullSystem) {
170 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
171 cause.ce = coProcID;
172 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
173 }
174 }

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192 protected:
193 Addr vaddr;
194 bool store;
195
196 AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
197 {}
198
199 void
167 {
168 MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
169 if (FullSystem) {
170 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
171 cause.ce = coProcID;
172 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
173 }
174 }

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192 protected:
193 Addr vaddr;
194 bool store;
195
196 AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
197 {}
198
199 void
200 invoke(ThreadContext * tc,
201 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
200 invoke(ThreadContext * tc, const StaticInstPtr &inst =
201 StaticInst::nullStaticInstPtr)
202 {
203 MipsFault<T>::invoke(tc, inst);
204 if (FullSystem)
205 tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
206 }
207};
208
209class AddressErrorFault : public AddressFault<AddressErrorFault>

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245 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
246
247 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
248 context.badVPN2 = this->vpn >> 2;
249 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
250 }
251
252 void
202 {
203 MipsFault<T>::invoke(tc, inst);
204 if (FullSystem)
205 tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
206 }
207};
208
209class AddressErrorFault : public AddressFault<AddressErrorFault>

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245 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
246
247 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
248 context.badVPN2 = this->vpn >> 2;
249 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
250 }
251
252 void
253 invoke(ThreadContext * tc,
254 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
253 invoke(ThreadContext * tc, const StaticInstPtr &inst =
254 StaticInst::nullStaticInstPtr)
255 {
256 if (FullSystem) {
257 DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name());
258 Addr vect = this->vect(tc);
259 setTlbExceptionState(tc, this->code());
260 tc->pcState(vect);
261 } else {
262 AddressFault<T>::invoke(tc, inst);

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256 if (FullSystem) {
257 DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name());
258 Addr vect = this->vect(tc);
259 setTlbExceptionState(tc, this->code());
260 tc->pcState(vect);
261 } else {
262 AddressFault<T>::invoke(tc, inst);

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