faults.hh (8591:8f23aeaf6a91) faults.hh (8696:642f83fafffb)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Korey Sewell
31 * Jaidev Patwardhan
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Korey Sewell
31 * Jaidev Patwardhan
32 * Zhengxing Li
33 * Deyuan Guo
32 */
33
34#ifndef __MIPS_FAULTS_HH__
35#define __MIPS_FAULTS_HH__
36
37#include "arch/mips/pra_constants.hh"
38#include "cpu/thread_context.hh"
39#include "debug/MipsPRA.hh"

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82
83 void setExceptionState(ThreadContext *, uint8_t);
84
85 virtual FaultVect offset(ThreadContext *tc) const = 0;
86 virtual ExcCode code() const = 0;
87 virtual FaultVect base(ThreadContext *tc) const
88 {
89 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
34 */
35
36#ifndef __MIPS_FAULTS_HH__
37#define __MIPS_FAULTS_HH__
38
39#include "arch/mips/pra_constants.hh"
40#include "cpu/thread_context.hh"
41#include "debug/MipsPRA.hh"

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84
85 void setExceptionState(ThreadContext *, uint8_t);
86
87 virtual FaultVect offset(ThreadContext *tc) const = 0;
88 virtual ExcCode code() const = 0;
89 virtual FaultVect base(ThreadContext *tc) const
90 {
91 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
90 if (status.bev)
92 if (!status.bev)
91 return tc->readMiscReg(MISCREG_EBASE);
92 else
93 return 0xbfc00200;
94 }
95
96 FaultVect
97 vect(ThreadContext *tc) const
98 {

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161 void
162 invoke(ThreadContext * tc,
163 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
164 {
165 MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
166 if (FULL_SYSTEM) {
167 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
168 cause.ce = coProcID;
93 return tc->readMiscReg(MISCREG_EBASE);
94 else
95 return 0xbfc00200;
96 }
97
98 FaultVect
99 vect(ThreadContext *tc) const
100 {

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163 void
164 invoke(ThreadContext * tc,
165 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
166 {
167 MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
168 if (FULL_SYSTEM) {
169 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
170 cause.ce = coProcID;
169 tc->setMiscReg(MISCREG_CAUSE, cause);
171 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
170 }
171 }
172};
173
174class InterruptFault : public MipsFault<InterruptFault>
175{
176 public:
177 FaultVect
178 offset(ThreadContext *tc) const
179 {
180 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
172 }
173 }
174};
175
176class InterruptFault : public MipsFault<InterruptFault>
177{
178 public:
179 FaultVect
180 offset(ThreadContext *tc) const
181 {
182 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
181 return cause.iv ? 0x200 : 0x000;
183 // offset 0x200 for release 2, 0x180 for release 1.
184 return cause.iv ? 0x200 : 0x180;
182 }
183};
184
185template <typename T>
186class AddressFault : public MipsFault<T>
187{
188 protected:
189 Addr vaddr;

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245 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
246 }
247
248 void
249 invoke(ThreadContext * tc,
250 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
251 {
252 if (FULL_SYSTEM) {
185 }
186};
187
188template <typename T>
189class AddressFault : public MipsFault<T>
190{
191 protected:
192 Addr vaddr;

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248 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
249 }
250
251 void
252 invoke(ThreadContext * tc,
253 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
254 {
255 if (FULL_SYSTEM) {
253 DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
254 tc->pcState(this->vect(tc));
256 DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name());
257 Addr vect = this->vect(tc);
255 setTlbExceptionState(tc, this->code());
258 setTlbExceptionState(tc, this->code());
259 tc->pcState(vect);
256 } else {
257 AddressFault<T>::invoke(tc, inst);
258 }
259 }
260
261 ExcCode
262 code() const
263 {

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261 AddressFault<T>::invoke(tc, inst);
262 }
263 }
264
265 ExcCode
266 code() const
267 {

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