1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Gabe Black 30 * Korey Sewell 31 * Jaidev Patwardhan 32 */ 33 34#ifndef __MIPS_FAULTS_HH__ 35#define __MIPS_FAULTS_HH__ 36 37#include "arch/mips/pra_constants.hh" 38#include "cpu/thread_context.hh" 39#include "debug/MipsPRA.hh" 40#include "sim/faults.hh" 41 42namespace MipsISA 43{ 44 45typedef const Addr FaultVect; 46
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47enum ExcCode { 48 // A dummy value to use when the code isn't defined or doesn't matter. 49 ExcCodeDummy = 0, 50 51 ExcCodeInt = 0, 52 ExcCodeMod = 1, 53 ExcCodeTlbL = 2, 54 ExcCodeTlbS = 3, 55 ExcCodeAdEL = 4, 56 ExcCodeAdES = 5, 57 ExcCodeIBE = 6, 58 ExcCodeDBE = 7, 59 ExcCodeSys = 8, 60 ExcCodeBp = 9, 61 ExcCodeRI = 10, 62 ExcCodeCpU = 11, 63 ExcCodeOv = 12, 64 ExcCodeTr = 13, 65 ExcCodeC2E = 18, 66 ExcCodeMDMX = 22, 67 ExcCodeWatch = 23, 68 ExcCodeMCheck = 24, 69 ExcCodeThread = 25, 70 ExcCodeCacheErr = 30 71}; 72 |
73class MipsFaultBase : public FaultBase 74{ 75 public: 76 struct FaultVals 77 { 78 const FaultName name;
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53 const FaultVect vect;
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79 const FaultVect offset; 80 const ExcCode code; |
81 }; 82
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56#if FULL_SYSTEM
57 void invoke(ThreadContext * tc,
58 StaticInst::StaticInstPtr inst = StaticInst::nullStaticInstPtr)
59 {}
60#endif
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83 void setExceptionState(ThreadContext *, uint8_t);
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84 85 virtual FaultVect offset(ThreadContext *tc) const = 0; 86 virtual ExcCode code() const = 0; 87 virtual FaultVect base(ThreadContext *tc) const 88 { 89 StatusReg status = tc->readMiscReg(MISCREG_STATUS); 90 if (status.bev) 91 return tc->readMiscReg(MISCREG_EBASE); 92 else 93 return 0xbfc00200; 94 } 95 96 FaultVect 97 vect(ThreadContext *tc) const 98 { 99 return base(tc) + offset(tc); 100 } 101 102 void invoke(ThreadContext * tc, 103 StaticInstPtr inst = StaticInst::nullStaticInstPtr); |
104}; 105 106template <typename T> 107class MipsFault : public MipsFaultBase 108{ 109 protected: 110 static FaultVals vals; 111 public: 112 FaultName name() const { return vals.name; }
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71 FaultVect vect() const { return vals.vect; }
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113 FaultVect offset(ThreadContext *tc) const { return vals.offset; } 114 ExcCode code() const { return vals.code; } |
115}; 116
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74template <typename T>
75class AddressFault : public MipsFault<T>
76{
77 protected:
78 Addr vaddr;
79 bool store;
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117class SystemCallFault : public MipsFault<SystemCallFault> {}; 118class ReservedInstructionFault : public MipsFault<ReservedInstructionFault> {}; 119class ThreadFault : public MipsFault<ThreadFault> {}; 120class IntegerOverflowFault : public MipsFault<IntegerOverflowFault> {}; 121class TrapFault : public MipsFault<TrapFault> {}; 122class BreakpointFault : public MipsFault<BreakpointFault> {}; 123class DspStateDisabledFault : public MipsFault<DspStateDisabledFault> {}; |
124
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81 AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
82 {}
83};
84
85template <typename T>
86class TlbFault : public AddressFault<T>
87{
88 protected:
89 Addr asid;
90 Addr vpn;
91
92 TlbFault(Addr _asid, Addr _vaddr, Addr _vpn, bool _store) :
93 AddressFault<T>(_vaddr, _store), asid(_asid), vpn(_vpn)
94 {}
95
96 void
97 setTlbExceptionState(ThreadContext *tc, uint8_t excCode)
98 {
99 DPRINTF(MipsPRA, "%s encountered.\n", name());
100 this->setExceptionState(tc, excCode);
101
102 tc->setMiscRegNoEffect(MISCREG_BADVADDR, this->vaddr);
103 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
104 entryHi.asid = this->asid;
105 entryHi.vpn2 = this->vpn >> 2;
106 entryHi.vpn2x = this->vpn & 0x3;
107 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
108
109 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
110 context.badVPN2 = this->vpn >> 2;
111 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
112 }
113};
114
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125class MachineCheckFault : public MipsFault<MachineCheckFault> 126{ 127 public:
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118 bool isMachineCheckFault() {return true;}
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128 bool isMachineCheckFault() { return true; } |
129}; 130 131static inline Fault genMachineCheckFault() 132{ 133 return new MachineCheckFault; 134} 135
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126class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
127{
128 public:
129 bool isNonMaskableInterrupt() {return true;}
130};
131
132class AddressErrorFault : public AddressFault<AddressErrorFault>
133{
134 public:
135 AddressErrorFault(Addr _vaddr, bool _store) :
136 AddressFault<AddressErrorFault>(_vaddr, _store)
137 {}
138#if FULL_SYSTEM
139 void invoke(ThreadContext * tc,
140 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
141#endif
142
143};
144
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136class ResetFault : public MipsFault<ResetFault> 137{ 138 public: 139 void invoke(ThreadContext * tc, 140 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 141 142}; 143
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153class SystemCallFault : public MipsFault<SystemCallFault>
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144class SoftResetFault : public MipsFault<SoftResetFault> |
145{ 146 public:
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156#if FULL_SYSTEM
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147 void invoke(ThreadContext * tc, 148 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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159#endif
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149}; 150
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162class SoftResetFault : public MipsFault<SoftResetFault>
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151class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt> |
152{ 153 public: 154 void invoke(ThreadContext * tc, 155 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 156}; 157 158class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault> 159{ 160 protected: 161 int coProcID; 162 public: 163 CoprocessorUnusableFault(int _procid) : coProcID(_procid) 164 {} 165
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177 void invoke(ThreadContext * tc,
178 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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166 void 167 invoke(ThreadContext * tc, 168 StaticInstPtr inst = StaticInst::nullStaticInstPtr) 169 { 170 MipsFault<CoprocessorUnusableFault>::invoke(tc, inst); 171 if (FULL_SYSTEM) { 172 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 173 cause.ce = coProcID; 174 tc->setMiscReg(MISCREG_CAUSE, cause); 175 } 176 } |
177}; 178
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181class ReservedInstructionFault : public MipsFault<ReservedInstructionFault>
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179class InterruptFault : public MipsFault<InterruptFault> |
180{ 181 public:
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184 void invoke(ThreadContext * tc,
185 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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182 FaultVect 183 offset(ThreadContext *tc) const 184 { 185 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); 186 return cause.iv ? 0x200 : 0x000; 187 } |
188}; 189
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188class ThreadFault : public MipsFault<ThreadFault>
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190template <typename T> 191class AddressFault : public MipsFault<T> |
192{
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190 public:
191 void invoke(ThreadContext * tc,
192 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
193};
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193 protected: 194 Addr vaddr; 195 bool store; |
196
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195class IntegerOverflowFault : public MipsFault<IntegerOverflowFault>
196{
197 public:
198#if FULL_SYSTEM
199 void invoke(ThreadContext * tc,
200 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
201#endif
202};
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197 AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store) 198 {} |
199
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204class InterruptFault : public MipsFault<InterruptFault>
205{
206 public:
207#if FULL_SYSTEM
208 void invoke(ThreadContext * tc,
209 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
210#endif
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200 void 201 invoke(ThreadContext * tc, 202 StaticInstPtr inst = StaticInst::nullStaticInstPtr) 203 { 204 MipsFault<T>::invoke(tc, inst); 205 if (FULL_SYSTEM) 206 tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr); 207 } |
208}; 209
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213class TrapFault : public MipsFault<TrapFault>
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210class AddressErrorFault : public AddressFault<AddressErrorFault> |
211{ 212 public:
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216#if FULL_SYSTEM
217 void invoke(ThreadContext * tc,
218 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
219#endif
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213 AddressErrorFault(Addr _vaddr, bool _store) : 214 AddressFault<AddressErrorFault>(_vaddr, _store) 215 {} 216 217 ExcCode 218 code() const 219 { 220 return store ? ExcCodeAdES : ExcCodeAdEL; 221 } 222 |
223}; 224
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222class BreakpointFault : public MipsFault<BreakpointFault>
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225template <typename T> 226class TlbFault : public AddressFault<T> |
227{
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224 public:
225#if FULL_SYSTEM
226 void invoke(ThreadContext * tc,
227 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
228#endif
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228 protected: 229 Addr asid; 230 Addr vpn; 231 232 TlbFault(Addr _asid, Addr _vaddr, Addr _vpn, bool _store) : 233 AddressFault<T>(_vaddr, _store), asid(_asid), vpn(_vpn) 234 {} 235 236 void 237 setTlbExceptionState(ThreadContext *tc, uint8_t excCode) 238 { 239 this->setExceptionState(tc, excCode); 240 241 tc->setMiscRegNoEffect(MISCREG_BADVADDR, this->vaddr); 242 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 243 entryHi.asid = this->asid; 244 entryHi.vpn2 = this->vpn >> 2; 245 entryHi.vpn2x = this->vpn & 0x3; 246 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 247 248 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 249 context.badVPN2 = this->vpn >> 2; 250 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 251 } 252 253 void 254 invoke(ThreadContext * tc, 255 StaticInstPtr inst = StaticInst::nullStaticInstPtr) 256 { 257 if (FULL_SYSTEM) { 258 DPRINTF(MipsPRA, "Fault %s encountered.\n", name()); 259 tc->pcState(this->vect(tc)); 260 setTlbExceptionState(tc, this->code()); 261 } else { 262 AddressFault<T>::invoke(tc, inst); 263 } 264 } 265 266 ExcCode 267 code() const 268 { 269 return this->store ? ExcCodeTlbS : ExcCodeTlbL; 270 } |
271}; 272 273class TlbRefillFault : public TlbFault<TlbRefillFault> 274{ 275 public: 276 TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool store) : 277 TlbFault<TlbRefillFault>(asid, vaddr, vpn, store) 278 {}
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237#if FULL_SYSTEM
238 void invoke(ThreadContext * tc,
239 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
240#endif
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279 280 FaultVect 281 offset(ThreadContext *tc) const 282 { 283 StatusReg status = tc->readMiscReg(MISCREG_STATUS); 284 return status.exl ? 0x180 : 0x000; 285 } |
286}; 287 288class TlbInvalidFault : public TlbFault<TlbInvalidFault> 289{ 290 public: 291 TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool store) : 292 TlbFault<TlbInvalidFault>(asid, vaddr, vpn, store) 293 {}
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249#if FULL_SYSTEM
250 void invoke(ThreadContext * tc,
251 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
252#endif
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294}; 295 296class TlbModifiedFault : public TlbFault<TlbModifiedFault> 297{ 298 public: 299 TlbModifiedFault(Addr asid, Addr vaddr, Addr vpn) : 300 TlbFault<TlbModifiedFault>(asid, vaddr, vpn, false) 301 {}
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261#if FULL_SYSTEM
262 void invoke(ThreadContext * tc,
263 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
264#endif
265};
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302
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267class DspStateDisabledFault : public MipsFault<DspStateDisabledFault>
268{
269 public:
270 void invoke(ThreadContext * tc,
271 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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303 ExcCode code() const { return vals.code; } |
304}; 305 306} // namespace MipsISA 307 308#endif // __MIPS_FAULTS_HH__
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