1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Korey Sewell
31 * Jaidev Patwardhan
32 * Zhengxing Li
33 * Deyuan Guo
32 */
33
34#ifndef __MIPS_FAULTS_HH__
35#define __MIPS_FAULTS_HH__
36
37#include "arch/mips/pra_constants.hh"
38#include "cpu/thread_context.hh"
39#include "debug/MipsPRA.hh"
40#include "sim/faults.hh"
41#include "sim/full_system.hh"
42
43namespace MipsISA
44{
45
46typedef const Addr FaultVect;
47
48enum ExcCode {
49 // A dummy value to use when the code isn't defined or doesn't matter.

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83
84 void setExceptionState(ThreadContext *, uint8_t);
85
86 virtual FaultVect offset(ThreadContext *tc) const = 0;
87 virtual ExcCode code() const = 0;
88 virtual FaultVect base(ThreadContext *tc) const
89 {
90 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
92 if (!status.bev)
91 if (status.bev)
92 return tc->readMiscReg(MISCREG_EBASE);
93 else
94 return 0xbfc00200;
95 }
96
97 FaultVect
98 vect(ThreadContext *tc) const
99 {

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159 CoprocessorUnusableFault(int _procid) : coProcID(_procid)
160 {}
161
162 void
163 invoke(ThreadContext * tc,
164 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
165 {
166 MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
168 if (FULL_SYSTEM) {
167 if (FullSystem) {
168 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
169 cause.ce = coProcID;
171 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
170 tc->setMiscReg(MISCREG_CAUSE, cause);
171 }
172 }
173};
174
175class InterruptFault : public MipsFault<InterruptFault>
176{
177 public:
178 FaultVect
179 offset(ThreadContext *tc) const
180 {
181 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
183 // offset 0x200 for release 2, 0x180 for release 1.
184 return cause.iv ? 0x200 : 0x180;
182 return cause.iv ? 0x200 : 0x000;
183 }
184};
185
186template <typename T>
187class AddressFault : public MipsFault<T>
188{
189 protected:
190 Addr vaddr;
191 bool store;
192
193 AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
194 {}
195
196 void
197 invoke(ThreadContext * tc,
198 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
199 {
200 MipsFault<T>::invoke(tc, inst);
203 if (FULL_SYSTEM)
201 if (FullSystem)
202 tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
203 }
204};
205
206class AddressErrorFault : public AddressFault<AddressErrorFault>
207{
208 public:
209 AddressErrorFault(Addr _vaddr, bool _store) :

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245 context.badVPN2 = this->vpn >> 2;
246 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
247 }
248
249 void
250 invoke(ThreadContext * tc,
251 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
252 {
255 if (FULL_SYSTEM) {
256 DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name());
257 Addr vect = this->vect(tc);
253 if (FullSystem) {
254 DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
255 tc->pcState(this->vect(tc));
256 setTlbExceptionState(tc, this->code());
259 tc->pcState(vect);
257 } else {
258 AddressFault<T>::invoke(tc, inst);
259 }
260 }
261
262 ExcCode
263 code() const
264 {

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291
292class TlbModifiedFault : public TlbFault<TlbModifiedFault>
293{
294 public:
295 TlbModifiedFault(Addr asid, Addr vaddr, Addr vpn) :
296 TlbFault<TlbModifiedFault>(asid, vaddr, vpn, false)
297 {}
298
302 ExcCode code() const { return MipsFault<TlbModifiedFault>::code(); }
299 ExcCode code() const { return vals.code; }
300};
301
302} // namespace MipsISA
303
304#endif // __MIPS_FAULTS_HH__