1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 20 unchanged lines hidden (view full) --- 29 * Authors: Gabe Black 30 * Korey Sewell 31 * Jaidev Patwardhan 32 */ 33 34#ifndef __MIPS_FAULTS_HH__ 35#define __MIPS_FAULTS_HH__ 36 |
37#include "arch/mips/pra_constants.hh" 38#include "cpu/thread_context.hh" 39#include "debug/MipsPRA.hh" |
40#include "sim/faults.hh" 41 42namespace MipsISA 43{ 44 45typedef const Addr FaultVect; 46 47class MipsFaultBase : public FaultBase 48{ 49 protected: 50 virtual bool skipFaultingInstruction() {return false;} 51 virtual bool setRestartAddress() {return true;} 52 public: 53 struct FaultVals 54 { 55 const FaultName name; 56 const FaultVect vect; 57 }; 58 |
59#if FULL_SYSTEM 60 void invoke(ThreadContext * tc, 61 StaticInst::StaticInstPtr inst = StaticInst::nullStaticInstPtr) 62 {} 63 void setHandlerPC(Addr, ThreadContext *); 64#endif 65 void setExceptionState(ThreadContext *, uint8_t); 66}; 67 68template <typename T> 69class MipsFault : public MipsFaultBase 70{ 71 protected: 72 static FaultVals vals; 73 public: 74 FaultName name() const { return vals.name; } 75 FaultVect vect() const { return vals.vect; } 76}; 77 |
78template <typename T> 79class AddressFault : public MipsFault<T> 80{ 81 protected: 82 Addr vaddr; 83 bool store; 84 85 AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store) 86 {} 87}; 88 89template <typename T> 90class TlbFault : public AddressFault<T> 91{ 92 protected: 93 Addr asid; 94 Addr vpn; 95 96 TlbFault(Addr _asid, Addr _vaddr, Addr _vpn, bool _store) : 97 AddressFault<T>(_vaddr, _store), asid(_asid), vpn(_vpn) 98 {} 99 100 void 101 setTlbExceptionState(ThreadContext *tc, uint8_t excCode) 102 { 103 DPRINTF(MipsPRA, "%s encountered.\n", name()); 104 this->setExceptionState(tc, excCode); 105 106 tc->setMiscRegNoEffect(MISCREG_BADVADDR, this->vaddr); 107 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 108 entryHi.asid = this->asid; 109 entryHi.vpn2 = this->vpn >> 2; 110 entryHi.vpn2x = this->vpn & 0x3; 111 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); 112 113 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 114 context.badVPN2 = this->vpn >> 2; 115 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); 116 } 117}; 118 |
119class MachineCheckFault : public MipsFault<MachineCheckFault> 120{ 121 public: 122 bool isMachineCheckFault() {return true;} 123}; 124 125static inline Fault genMachineCheckFault() 126{ 127 return new MachineCheckFault; 128} 129 130class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt> 131{ 132 public: 133 bool isNonMaskableInterrupt() {return true;} 134}; 135 |
136class AddressErrorFault : public AddressFault<AddressErrorFault> |
137{ |
138 public: |
139 AddressErrorFault(Addr _vaddr, bool _store) : 140 AddressFault<AddressErrorFault>(_vaddr, _store) |
141 {} 142#if FULL_SYSTEM 143 void invoke(ThreadContext * tc, 144 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 145#endif 146 147}; 148 --- 82 unchanged lines hidden (view full) --- 231{ 232 public: 233#if FULL_SYSTEM 234 void invoke(ThreadContext * tc, 235 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 236#endif 237}; 238 |
239class TlbRefillFault : public TlbFault<TlbRefillFault> |
240{ |
241 public: |
242 TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool store) : 243 TlbFault<TlbRefillFault>(asid, vaddr, vpn, store) 244 {} |
245#if FULL_SYSTEM 246 void invoke(ThreadContext * tc, 247 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 248#endif 249}; 250 |
251class TlbInvalidFault : public TlbFault<TlbInvalidFault> |
252{ |
253 public: |
254 TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool store) : 255 TlbFault<TlbInvalidFault>(asid, vaddr, vpn, store) 256 {} |
257#if FULL_SYSTEM 258 void invoke(ThreadContext * tc, 259 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 260#endif 261}; 262 |
263class TlbModifiedFault : public TlbFault<TlbModifiedFault> |
264{ 265 public: |
266 TlbModifiedFault(Addr asid, Addr vaddr, Addr vpn) : 267 TlbFault<TlbModifiedFault>(asid, vaddr, vpn, false) 268 {} |
269#if FULL_SYSTEM 270 void invoke(ThreadContext * tc, 271 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 272#endif 273}; 274 275class DspStateDisabledFault : public MipsFault<DspStateDisabledFault> 276{ 277 public: 278 void invoke(ThreadContext * tc, 279 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 280}; 281 282} // namespace MipsISA 283 284#endif // __MIPS_FAULTS_HH__ |