1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Korey Sewell
31 * Jaidev Patwardhan
32 */
33
34#ifndef __MIPS_FAULTS_HH__
35#define __MIPS_FAULTS_HH__
36
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Korey Sewell
31 * Jaidev Patwardhan
32 */
33
34#ifndef __MIPS_FAULTS_HH__
35#define __MIPS_FAULTS_HH__
36
|
| 37#include "arch/mips/pra_constants.hh"
38#include "cpu/thread_context.hh"
39#include "debug/MipsPRA.hh"
|
37#include "sim/faults.hh"
38
39namespace MipsISA
40{
41
42typedef const Addr FaultVect;
43
44class MipsFaultBase : public FaultBase
45{
46 protected:
47 virtual bool skipFaultingInstruction() {return false;}
48 virtual bool setRestartAddress() {return true;}
49 public:
50 struct FaultVals
51 {
52 const FaultName name;
53 const FaultVect vect;
54 };
55
| 40#include "sim/faults.hh"
41
42namespace MipsISA
43{
44
45typedef const Addr FaultVect;
46
47class MipsFaultBase : public FaultBase
48{
49 protected:
50 virtual bool skipFaultingInstruction() {return false;}
51 virtual bool setRestartAddress() {return true;}
52 public:
53 struct FaultVals
54 {
55 const FaultName name;
56 const FaultVect vect;
57 };
58
|
56 Addr badVAddr;
57 Addr entryHiAsid;
58 Addr entryHiVPN2;
59 Addr entryHiVPN2X;
60 Addr contextBadVPN2;
| |
61#if FULL_SYSTEM
62 void invoke(ThreadContext * tc,
63 StaticInst::StaticInstPtr inst = StaticInst::nullStaticInstPtr)
64 {}
65 void setHandlerPC(Addr, ThreadContext *);
66#endif
67 void setExceptionState(ThreadContext *, uint8_t);
68};
69
70template <typename T>
71class MipsFault : public MipsFaultBase
72{
73 protected:
74 static FaultVals vals;
75 public:
76 FaultName name() const { return vals.name; }
77 FaultVect vect() const { return vals.vect; }
78};
79
| 59#if FULL_SYSTEM
60 void invoke(ThreadContext * tc,
61 StaticInst::StaticInstPtr inst = StaticInst::nullStaticInstPtr)
62 {}
63 void setHandlerPC(Addr, ThreadContext *);
64#endif
65 void setExceptionState(ThreadContext *, uint8_t);
66};
67
68template <typename T>
69class MipsFault : public MipsFaultBase
70{
71 protected:
72 static FaultVals vals;
73 public:
74 FaultName name() const { return vals.name; }
75 FaultVect vect() const { return vals.vect; }
76};
77
|
| 78template <typename T>
79class AddressFault : public MipsFault<T>
80{
81 protected:
82 Addr vaddr;
83 bool store;
84
85 AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
86 {}
87};
88
89template <typename T>
90class TlbFault : public AddressFault<T>
91{
92 protected:
93 Addr asid;
94 Addr vpn;
95
96 TlbFault(Addr _asid, Addr _vaddr, Addr _vpn, bool _store) :
97 AddressFault<T>(_vaddr, _store), asid(_asid), vpn(_vpn)
98 {}
99
100 void
101 setTlbExceptionState(ThreadContext *tc, uint8_t excCode)
102 {
103 DPRINTF(MipsPRA, "%s encountered.\n", name());
104 this->setExceptionState(tc, excCode);
105
106 tc->setMiscRegNoEffect(MISCREG_BADVADDR, this->vaddr);
107 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
108 entryHi.asid = this->asid;
109 entryHi.vpn2 = this->vpn >> 2;
110 entryHi.vpn2x = this->vpn & 0x3;
111 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
112
113 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
114 context.badVPN2 = this->vpn >> 2;
115 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
116 }
117};
118
|
80class MachineCheckFault : public MipsFault<MachineCheckFault>
81{
82 public:
83 bool isMachineCheckFault() {return true;}
84};
85
86static inline Fault genMachineCheckFault()
87{
88 return new MachineCheckFault;
89}
90
91class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
92{
93 public:
94 bool isNonMaskableInterrupt() {return true;}
95};
96
| 119class MachineCheckFault : public MipsFault<MachineCheckFault>
120{
121 public:
122 bool isMachineCheckFault() {return true;}
123};
124
125static inline Fault genMachineCheckFault()
126{
127 return new MachineCheckFault;
128}
129
130class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
131{
132 public:
133 bool isNonMaskableInterrupt() {return true;}
134};
135
|
97class AddressErrorFault : public MipsFault<AddressErrorFault>
| 136class AddressErrorFault : public AddressFault<AddressErrorFault>
|
98{
| 137{
|
99 protected:
100 Addr vaddr;
101 bool store;
| |
102 public:
| 138 public:
|
103 AddressErrorFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
| 139 AddressErrorFault(Addr _vaddr, bool _store) :
140 AddressFault<AddressErrorFault>(_vaddr, _store)
|
104 {}
105#if FULL_SYSTEM
106 void invoke(ThreadContext * tc,
107 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
108#endif
109
110};
111
112class ResetFault : public MipsFault<ResetFault>
113{
114 public:
115 void invoke(ThreadContext * tc,
116 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
117
118};
119
120class SystemCallFault : public MipsFault<SystemCallFault>
121{
122 public:
123#if FULL_SYSTEM
124 void invoke(ThreadContext * tc,
125 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
126#endif
127};
128
129class SoftResetFault : public MipsFault<SoftResetFault>
130{
131 public:
132 void invoke(ThreadContext * tc,
133 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
134};
135
136class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
137{
138 protected:
139 int coProcID;
140 public:
141 CoprocessorUnusableFault(int _procid) : coProcID(_procid)
142 {}
143
144 void invoke(ThreadContext * tc,
145 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
146};
147
148class ReservedInstructionFault : public MipsFault<ReservedInstructionFault>
149{
150 public:
151 void invoke(ThreadContext * tc,
152 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
153};
154
155class ThreadFault : public MipsFault<ThreadFault>
156{
157 public:
158 void invoke(ThreadContext * tc,
159 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
160};
161
162class IntegerOverflowFault : public MipsFault<IntegerOverflowFault>
163{
164 protected:
165 bool skipFaultingInstruction() {return true;}
166 public:
167#if FULL_SYSTEM
168 void invoke(ThreadContext * tc,
169 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
170#endif
171};
172
173class InterruptFault : public MipsFault<InterruptFault>
174{
175 protected:
176 bool setRestartAddress() {return false;}
177 public:
178#if FULL_SYSTEM
179 void invoke(ThreadContext * tc,
180 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
181#endif
182};
183
184class TrapFault : public MipsFault<TrapFault>
185{
186 public:
187#if FULL_SYSTEM
188 void invoke(ThreadContext * tc,
189 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
190#endif
191};
192
193class BreakpointFault : public MipsFault<BreakpointFault>
194{
195 public:
196#if FULL_SYSTEM
197 void invoke(ThreadContext * tc,
198 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
199#endif
200};
201
| 141 {}
142#if FULL_SYSTEM
143 void invoke(ThreadContext * tc,
144 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
145#endif
146
147};
148
149class ResetFault : public MipsFault<ResetFault>
150{
151 public:
152 void invoke(ThreadContext * tc,
153 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
154
155};
156
157class SystemCallFault : public MipsFault<SystemCallFault>
158{
159 public:
160#if FULL_SYSTEM
161 void invoke(ThreadContext * tc,
162 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
163#endif
164};
165
166class SoftResetFault : public MipsFault<SoftResetFault>
167{
168 public:
169 void invoke(ThreadContext * tc,
170 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
171};
172
173class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
174{
175 protected:
176 int coProcID;
177 public:
178 CoprocessorUnusableFault(int _procid) : coProcID(_procid)
179 {}
180
181 void invoke(ThreadContext * tc,
182 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
183};
184
185class ReservedInstructionFault : public MipsFault<ReservedInstructionFault>
186{
187 public:
188 void invoke(ThreadContext * tc,
189 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
190};
191
192class ThreadFault : public MipsFault<ThreadFault>
193{
194 public:
195 void invoke(ThreadContext * tc,
196 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
197};
198
199class IntegerOverflowFault : public MipsFault<IntegerOverflowFault>
200{
201 protected:
202 bool skipFaultingInstruction() {return true;}
203 public:
204#if FULL_SYSTEM
205 void invoke(ThreadContext * tc,
206 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
207#endif
208};
209
210class InterruptFault : public MipsFault<InterruptFault>
211{
212 protected:
213 bool setRestartAddress() {return false;}
214 public:
215#if FULL_SYSTEM
216 void invoke(ThreadContext * tc,
217 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
218#endif
219};
220
221class TrapFault : public MipsFault<TrapFault>
222{
223 public:
224#if FULL_SYSTEM
225 void invoke(ThreadContext * tc,
226 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
227#endif
228};
229
230class BreakpointFault : public MipsFault<BreakpointFault>
231{
232 public:
233#if FULL_SYSTEM
234 void invoke(ThreadContext * tc,
235 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
236#endif
237};
238
|
202class TlbRefillFault : public MipsFault<TlbRefillFault>
| 239class TlbRefillFault : public TlbFault<TlbRefillFault>
|
203{
| 240{
|
204 protected:
205 bool store;
| |
206 public:
| 241 public:
|
207 TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool _store) :
208 store(_store)
209 {
210 entryHiAsid = asid;
211 entryHiVPN2 = vpn >> 2;
212 entryHiVPN2X = vpn & 0x3;
213 badVAddr = vaddr;
214 contextBadVPN2 = vpn >> 2;
215 }
| 242 TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool store) :
243 TlbFault<TlbRefillFault>(asid, vaddr, vpn, store)
244 {}
|
216#if FULL_SYSTEM
217 void invoke(ThreadContext * tc,
218 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
219#endif
220};
221
| 245#if FULL_SYSTEM
246 void invoke(ThreadContext * tc,
247 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
248#endif
249};
250
|
222class TlbInvalidFault : public MipsFault<TlbInvalidFault>
| 251class TlbInvalidFault : public TlbFault<TlbInvalidFault>
|
223{
| 252{
|
224 protected:
225 bool store;
| |
226 public:
| 253 public:
|
227 TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool _store) :
228 store(_store)
229 {
230 entryHiAsid = asid;
231 entryHiVPN2 = vpn >> 2;
232 entryHiVPN2X = vpn & 0x3;
233 badVAddr = vaddr;
234 contextBadVPN2 = vpn >> 2;
235 }
| 254 TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool store) :
255 TlbFault<TlbInvalidFault>(asid, vaddr, vpn, store)
256 {}
|
236#if FULL_SYSTEM
237 void invoke(ThreadContext * tc,
238 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
239#endif
240};
241
| 257#if FULL_SYSTEM
258 void invoke(ThreadContext * tc,
259 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
260#endif
261};
262
|
242class TLBModifiedFault : public MipsFault<TLBModifiedFault>
| 263class TlbModifiedFault : public TlbFault<TlbModifiedFault>
|
243{
244 public:
| 264{
265 public:
|
245 TLBModifiedFault(Addr asid, Addr vaddr, Addr vpn)
246 {
247 entryHiAsid = asid;
248 entryHiVPN2 = vpn >> 2;
249 entryHiVPN2X = vpn & 0x3;
250 badVAddr = vaddr;
251 contextBadVPN2 = vpn >> 2;
252 }
| 266 TlbModifiedFault(Addr asid, Addr vaddr, Addr vpn) :
267 TlbFault<TlbModifiedFault>(asid, vaddr, vpn, false)
268 {}
|
253#if FULL_SYSTEM
254 void invoke(ThreadContext * tc,
255 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
256#endif
257};
258
259class DspStateDisabledFault : public MipsFault<DspStateDisabledFault>
260{
261 public:
262 void invoke(ThreadContext * tc,
263 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
264};
265
266} // namespace MipsISA
267
268#endif // __MIPS_FAULTS_HH__
| 269#if FULL_SYSTEM
270 void invoke(ThreadContext * tc,
271 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
272#endif
273};
274
275class DspStateDisabledFault : public MipsFault<DspStateDisabledFault>
276{
277 public:
278 void invoke(ThreadContext * tc,
279 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
280};
281
282} // namespace MipsISA
283
284#endif // __MIPS_FAULTS_HH__
|