1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Korey Sewell
31 * Jaidev Patwardhan
32 * Zhengxing Li
33 * Deyuan Guo
34 */
35
36#ifndef __MIPS_FAULTS_HH__
37#define __MIPS_FAULTS_HH__
38
39#include "arch/mips/pra_constants.hh"
40#include "cpu/thread_context.hh"
41#include "debug/MipsPRA.hh"
42#include "sim/faults.hh"
43
44namespace MipsISA
45{
46
47typedef const Addr FaultVect;
48
49enum ExcCode {
50 // A dummy value to use when the code isn't defined or doesn't matter.

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84
85 void setExceptionState(ThreadContext *, uint8_t);
86
87 virtual FaultVect offset(ThreadContext *tc) const = 0;
88 virtual ExcCode code() const = 0;
89 virtual FaultVect base(ThreadContext *tc) const
90 {
91 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
92 if (!status.bev)
93 return tc->readMiscReg(MISCREG_EBASE);
94 else
95 return 0xbfc00200;
96 }
97
98 FaultVect
99 vect(ThreadContext *tc) const
100 {

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160 CoprocessorUnusableFault(int _procid) : coProcID(_procid)
161 {}
162
163 void
164 invoke(ThreadContext * tc,
165 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
166 {
167 MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
168 if (FULL_SYSTEM) {
169 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
170 cause.ce = coProcID;
171 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
172 }
173 }
174};
175
176class InterruptFault : public MipsFault<InterruptFault>
177{
178 public:
179 FaultVect
180 offset(ThreadContext *tc) const
181 {
182 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
183 // offset 0x200 for release 2, 0x180 for release 1.
184 return cause.iv ? 0x200 : 0x180;
185 }
186};
187
188template <typename T>
189class AddressFault : public MipsFault<T>
190{
191 protected:
192 Addr vaddr;
193 bool store;
194
195 AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
196 {}
197
198 void
199 invoke(ThreadContext * tc,
200 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
201 {
202 MipsFault<T>::invoke(tc, inst);
203 if (FULL_SYSTEM)
204 tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
205 }
206};
207
208class AddressErrorFault : public AddressFault<AddressErrorFault>
209{
210 public:
211 AddressErrorFault(Addr _vaddr, bool _store) :

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247 context.badVPN2 = this->vpn >> 2;
248 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
249 }
250
251 void
252 invoke(ThreadContext * tc,
253 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
254 {
255 if (FULL_SYSTEM) {
256 DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name());
257 Addr vect = this->vect(tc);
258 setTlbExceptionState(tc, this->code());
259 tc->pcState(vect);
260 } else {
261 AddressFault<T>::invoke(tc, inst);
262 }
263 }
264
265 ExcCode
266 code() const
267 {

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294
295class TlbModifiedFault : public TlbFault<TlbModifiedFault>
296{
297 public:
298 TlbModifiedFault(Addr asid, Addr vaddr, Addr vpn) :
299 TlbFault<TlbModifiedFault>(asid, vaddr, vpn, false)
300 {}
301
302 ExcCode code() const { return MipsFault<TlbModifiedFault>::code(); }
303};
304
305} // namespace MipsISA
306
307#endif // __MIPS_FAULTS_HH__