faults.cc (8809:bb10807da889) faults.cc (10417:710ee116eb68)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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126 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
127 cause.excCode = excCode;
128 cause.bd = delay_slot ? 1 : 0;
129 cause.ce = 0;
130 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
131}
132
133void
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 117 unchanged lines hidden (view full) ---

126 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
127 cause.excCode = excCode;
128 cause.bd = delay_slot ? 1 : 0;
129 cause.ce = 0;
130 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
131}
132
133void
134MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
134MipsFaultBase::invoke(ThreadContext *tc, const StaticInstPtr &inst)
135{
136 if (FullSystem) {
137 DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
138 setExceptionState(tc, code());
139 tc->pcState(vect(tc));
140 } else {
141 panic("Fault %s encountered.\n", name());
142 }
143}
144
145void
135{
136 if (FullSystem) {
137 DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
138 setExceptionState(tc, code());
139 tc->pcState(vect(tc));
140 } else {
141 panic("Fault %s encountered.\n", name());
142 }
143}
144
145void
146ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
146ResetFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
147{
148 if (FullSystem) {
149 DPRINTF(MipsPRA, "%s encountered.\n", name());
150 /* All reset activity must be invoked from here */
151 Addr handler = vect(tc);
152 tc->pcState(handler);
153 DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler);
154 }
155
156 // Set Coprocessor 1 (Floating Point) To Usable
157 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
158 status.cu.cu1 = 1;
159 tc->setMiscReg(MISCREG_STATUS, status);
160}
161
162void
147{
148 if (FullSystem) {
149 DPRINTF(MipsPRA, "%s encountered.\n", name());
150 /* All reset activity must be invoked from here */
151 Addr handler = vect(tc);
152 tc->pcState(handler);
153 DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler);
154 }
155
156 // Set Coprocessor 1 (Floating Point) To Usable
157 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
158 status.cu.cu1 = 1;
159 tc->setMiscReg(MISCREG_STATUS, status);
160}
161
162void
163SoftResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
163SoftResetFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
164{
165 panic("Soft reset not implemented.\n");
166}
167
168void
164{
165 panic("Soft reset not implemented.\n");
166}
167
168void
169NonMaskableInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
169NonMaskableInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
170{
171 panic("Non maskable interrupt not implemented.\n");
172}
173
174} // namespace MipsISA
175
170{
171 panic("Non maskable interrupt not implemented.\n");
172}
173
174} // namespace MipsISA
175