faults.cc (8798:adaa92be9037) faults.cc (8809:bb10807da889)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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90 { "Address Error", 0x180, ExcCodeDummy };
91
92template <> FaultVals MipsFault<TlbInvalidFault>::vals =
93 { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy };
94
95template <> FaultVals MipsFault<TlbRefillFault>::vals =
96 { "TLB Refill Exception", 0x180, ExcCodeDummy };
97
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 81 unchanged lines hidden (view full) ---

90 { "Address Error", 0x180, ExcCodeDummy };
91
92template <> FaultVals MipsFault<TlbInvalidFault>::vals =
93 { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy };
94
95template <> FaultVals MipsFault<TlbRefillFault>::vals =
96 { "TLB Refill Exception", 0x180, ExcCodeDummy };
97
98template <> FaultVals MipsFault::vals =
98template <> MipsFaultBase::FaultVals MipsFault<TlbModifiedFault>::vals =
99 { "TLB Modified Exception", 0x180, ExcCodeMod };
100
101void
102MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
103{
104 // modify SRS Ctl - Save CSS, put ESS into CSS
105 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
106 if (status.exl != 1 && status.bev != 1) {

--- 69 unchanged lines hidden --- 		99 { "TLB Modified Exception", 0x180, ExcCodeMod };
100
101void
102MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
103{
104 // modify SRS Ctl - Save CSS, put ESS into CSS
105 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
106 if (status.exl != 1 && status.bev != 1) {

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