faults.cc (8775:1e3ca5d77b53) faults.cc (8798:adaa92be9037)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Korey Sewell
31 * Jaidev Patwardhan
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 15 unchanged lines hidden (view full) ---

24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Korey Sewell
31 * Jaidev Patwardhan
32 * Zhengxing Li
33 * Deyuan Guo
32 */
33
34#include "arch/mips/faults.hh"
35#include "arch/mips/pra_constants.hh"
36#include "base/trace.hh"
37#include "cpu/base.hh"
38#include "cpu/thread_context.hh"
39#include "debug/MipsPRA.hh"

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113 status.exl = 1;
114 tc->setMiscRegNoEffect(MISCREG_STATUS, status);
115
116 // write EPC
117 PCState pc = tc->pcState();
118 DPRINTF(MipsPRA, "PC: %s\n", pc);
119 bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
120 tc->setMiscRegNoEffect(MISCREG_EPC,
34 */
35
36#include "arch/mips/faults.hh"
37#include "arch/mips/pra_constants.hh"
38#include "base/trace.hh"
39#include "cpu/base.hh"
40#include "cpu/thread_context.hh"
41#include "debug/MipsPRA.hh"

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115 status.exl = 1;
116 tc->setMiscRegNoEffect(MISCREG_STATUS, status);
117
118 // write EPC
119 PCState pc = tc->pcState();
120 DPRINTF(MipsPRA, "PC: %s\n", pc);
121 bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
122 tc->setMiscRegNoEffect(MISCREG_EPC,
121 pc.pc() - delay_slot ? sizeof(MachInst) : 0);
123 pc.pc() - (delay_slot ? sizeof(MachInst) : 0));
122
123 // Set Cause_EXCCODE field
124 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
125 cause.excCode = excCode;
126 cause.bd = delay_slot ? 1 : 0;
127 cause.ce = 0;
128 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
129}

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125 // Set Cause_EXCCODE field
126 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
127 cause.excCode = excCode;
128 cause.bd = delay_slot ? 1 : 0;
129 cause.ce = 0;
130 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
131}

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