faults.cc (8737:770ccf3af571) faults.cc (8738:66bf413b0d5b)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Korey Sewell
31 * Jaidev Patwardhan
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Korey Sewell
31 * Jaidev Patwardhan
32 * Zhengxing Li
33 * Deyuan Guo
34 */
35
36#include "arch/mips/faults.hh"
37#include "arch/mips/pra_constants.hh"
38#include "base/trace.hh"
39#include "cpu/base.hh"
40#include "cpu/thread_context.hh"
41#include "debug/MipsPRA.hh"

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93 { "Address Error", 0x180, ExcCodeDummy };
94
95template <> FaultVals MipsFault<TlbInvalidFault>::vals =
96 { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy };
97
98template <> FaultVals MipsFault<TlbRefillFault>::vals =
99 { "TLB Refill Exception", 0x180, ExcCodeDummy };
100
32 */
33
34#include "arch/mips/faults.hh"
35#include "arch/mips/pra_constants.hh"
36#include "base/trace.hh"
37#include "cpu/base.hh"
38#include "cpu/thread_context.hh"
39#include "debug/MipsPRA.hh"

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91 { "Address Error", 0x180, ExcCodeDummy };
92
93template <> FaultVals MipsFault<TlbInvalidFault>::vals =
94 { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy };
95
96template <> FaultVals MipsFault<TlbRefillFault>::vals =
97 { "TLB Refill Exception", 0x180, ExcCodeDummy };
98
101template <> MipsFaultBase::FaultVals MipsFault<TlbModifiedFault>::vals =
99template <> FaultVals MipsFault::vals =
102 { "TLB Modified Exception", 0x180, ExcCodeMod };
103
104void
105MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
106{
107 // modify SRS Ctl - Save CSS, put ESS into CSS
108 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
109 if (status.exl != 1 && status.bev != 1) {

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118 status.exl = 1;
119 tc->setMiscRegNoEffect(MISCREG_STATUS, status);
120
121 // write EPC
122 PCState pc = tc->pcState();
123 DPRINTF(MipsPRA, "PC: %s\n", pc);
124 bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
125 tc->setMiscRegNoEffect(MISCREG_EPC,
100 { "TLB Modified Exception", 0x180, ExcCodeMod };
101
102void
103MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
104{
105 // modify SRS Ctl - Save CSS, put ESS into CSS
106 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
107 if (status.exl != 1 && status.bev != 1) {

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116 status.exl = 1;
117 tc->setMiscRegNoEffect(MISCREG_STATUS, status);
118
119 // write EPC
120 PCState pc = tc->pcState();
121 DPRINTF(MipsPRA, "PC: %s\n", pc);
122 bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
123 tc->setMiscRegNoEffect(MISCREG_EPC,
126 pc.pc() - (delay_slot ? sizeof(MachInst) : 0));
124 pc.pc() - delay_slot ? sizeof(MachInst) : 0);
127
128 // Set Cause_EXCCODE field
129 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
130 cause.excCode = excCode;
131 cause.bd = delay_slot ? 1 : 0;
132 cause.ce = 0;
133 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
134}
135
136void
137MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
138{
125
126 // Set Cause_EXCCODE field
127 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
128 cause.excCode = excCode;
129 cause.bd = delay_slot ? 1 : 0;
130 cause.ce = 0;
131 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
132}
133
134void
135MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
136{
139 if (FULL_SYSTEM) {
137 if (FullSystem) {
140 DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
141 setExceptionState(tc, code());
142 tc->pcState(vect(tc));
143 } else {
144 panic("Fault %s encountered.\n", name());
145 }
146}
147
148void
149ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
150{
138 DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
139 setExceptionState(tc, code());
140 tc->pcState(vect(tc));
141 } else {
142 panic("Fault %s encountered.\n", name());
143 }
144}
145
146void
147ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
148{
151 if (FULL_SYSTEM) {
149 if (FullSystem) {
152 DPRINTF(MipsPRA, "%s encountered.\n", name());
153 /* All reset activity must be invoked from here */
154 Addr handler = vect(tc);
155 tc->pcState(handler);
156 DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler);
157 }
158
159 // Set Coprocessor 1 (Floating Point) To Usable

--- 19 unchanged lines hidden --- 		150 DPRINTF(MipsPRA, "%s encountered.\n", name());
151 /* All reset activity must be invoked from here */
152 Addr handler = vect(tc);
153 tc->pcState(handler);
154 DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler);
155 }
156
157 // Set Coprocessor 1 (Floating Point) To Usable

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