faults.cc (8577:37dbd858c367) | faults.cc (8578:dee1f3ab92e4) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 34 unchanged lines hidden (view full) --- 43#include "sim/process.hh" 44#endif 45 46namespace MipsISA 47{ 48 49typedef MipsFaultBase::FaultVals FaultVals; 50 | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 34 unchanged lines hidden (view full) --- 43#include "sim/process.hh" 44#endif 45 46namespace MipsISA 47{ 48 49typedef MipsFaultBase::FaultVals FaultVals; 50 |
51template <> FaultVals MipsFault<MachineCheckFault>::vals = 52 { "Machine Check", 0x0401 }; 53 54template <> FaultVals MipsFault<ResetFault>::vals = 55#if FULL_SYSTEM 56 { "Reset Fault", 0xBFC00000}; 57#else 58 { "Reset Fault", 0x001}; 59#endif 60 61template <> FaultVals MipsFault<AddressErrorFault>::vals = 62 { "Address Error", 0x0180 }; 63 | |
64template <> FaultVals MipsFault<SystemCallFault>::vals = | 51template <> FaultVals MipsFault<SystemCallFault>::vals = |
65 { "Syscall", 0x0180 }; | 52 { "Syscall", 0x180, ExcCodeSys }; |
66 | 53 |
67template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals = 68 { "Coprocessor Unusable Fault", 0x180 }; 69 | |
70template <> FaultVals MipsFault<ReservedInstructionFault>::vals = | 54template <> FaultVals MipsFault<ReservedInstructionFault>::vals = |
71 { "Reserved Instruction Fault", 0x0180 }; | 55 { "Reserved Instruction Fault", 0x180, ExcCodeRI }; |
72 73template <> FaultVals MipsFault<ThreadFault>::vals = | 56 57template <> FaultVals MipsFault<ThreadFault>::vals = |
74 { "Thread Fault", 0x00F1 }; | 58 { "Thread Fault", 0x180, ExcCodeDummy }; |
75 76template <> FaultVals MipsFault<IntegerOverflowFault>::vals = | 59 60template <> FaultVals MipsFault<IntegerOverflowFault>::vals = |
77 { "Integer Overflow Exception", 0x180 }; | 61 { "Integer Overflow Exception", 0x180, ExcCodeOv }; |
78 | 62 |
79template <> FaultVals MipsFault<InterruptFault>::vals = 80 { "interrupt", 0x0180 }; 81 | |
82template <> FaultVals MipsFault<TrapFault>::vals = | 63template <> FaultVals MipsFault<TrapFault>::vals = |
83 { "Trap", 0x0180 }; | 64 { "Trap", 0x180, ExcCodeTr }; |
84 85template <> FaultVals MipsFault<BreakpointFault>::vals = | 65 66template <> FaultVals MipsFault<BreakpointFault>::vals = |
86 { "Breakpoint", 0x0180 }; | 67 { "Breakpoint", 0x180, ExcCodeBp }; |
87 | 68 |
69template <> FaultVals MipsFault<DspStateDisabledFault>::vals = 70 { "DSP Disabled Fault", 0x180, ExcCodeDummy }; 71 72template <> FaultVals MipsFault<MachineCheckFault>::vals = 73 { "Machine Check", 0x180, ExcCodeMCheck }; 74 75template <> FaultVals MipsFault<ResetFault>::vals = 76 { "Reset Fault", 0x000, ExcCodeDummy }; 77 78template <> FaultVals MipsFault<SoftResetFault>::vals = 79 { "Soft Reset Fault", 0x000, ExcCodeDummy }; 80 81template <> FaultVals MipsFault<NonMaskableInterrupt>::vals = 82 { "Non Maskable Interrupt", 0x000, ExcCodeDummy }; 83 84template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals = 85 { "Coprocessor Unusable Fault", 0x180, ExcCodeCpU }; 86 87template <> FaultVals MipsFault<InterruptFault>::vals = 88 { "Interrupt", 0x000, ExcCodeInt }; 89 90template <> FaultVals MipsFault<AddressErrorFault>::vals = 91 { "Address Error", 0x180, ExcCodeDummy }; 92 |
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88template <> FaultVals MipsFault<TlbInvalidFault>::vals = | 93template <> FaultVals MipsFault<TlbInvalidFault>::vals = |
89 { "Invalid TLB Entry Exception", 0x0180 }; | 94 { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy }; |
90 91template <> FaultVals MipsFault<TlbRefillFault>::vals = | 95 96template <> FaultVals MipsFault<TlbRefillFault>::vals = |
92 { "TLB Refill Exception", 0x0180 }; | 97 { "TLB Refill Exception", 0x180, ExcCodeDummy }; |
93 94template <> FaultVals MipsFault<TlbModifiedFault>::vals = | 98 99template <> FaultVals MipsFault<TlbModifiedFault>::vals = |
95 { "TLB Modified Exception", 0x0180 }; | 100 { "TLB Modified Exception", 0x180, ExcCodeMod }; |
96 | 101 |
97template <> FaultVals MipsFault<DspStateDisabledFault>::vals = 98 { "DSP Disabled Fault", 0x001a }; 99 | |
100void 101MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode) 102{ 103 // modify SRS Ctl - Save CSS, put ESS into CSS 104 StatusReg status = tc->readMiscReg(MISCREG_STATUS); 105 if (status.exl != 1 && status.bev != 1) { 106 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set 107 SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL); --- 16 unchanged lines hidden (view full) --- 124 // Set Cause_EXCCODE field 125 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 126 cause.excCode = excCode; 127 cause.bd = delay_slot ? 1 : 0; 128 cause.ce = 0; 129 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 130} 131 | 102void 103MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode) 104{ 105 // modify SRS Ctl - Save CSS, put ESS into CSS 106 StatusReg status = tc->readMiscReg(MISCREG_STATUS); 107 if (status.exl != 1 && status.bev != 1) { 108 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set 109 SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL); --- 16 unchanged lines hidden (view full) --- 126 // Set Cause_EXCCODE field 127 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 128 cause.excCode = excCode; 129 cause.bd = delay_slot ? 1 : 0; 130 cause.ce = 0; 131 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 132} 133 |
132#if FULL_SYSTEM 133 | |
134void | 134void |
135IntegerOverflowFault::invoke(ThreadContext *tc, StaticInstPtr inst) | 135MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst) |
136{ | 136{ |
137 DPRINTF(MipsPRA, "%s encountered.\n", name()); 138 setExceptionState(tc, 0xC); 139 140 // Set new PC 141 StatusReg status = tc->readMiscReg(MISCREG_STATUS); 142 if (!status.bev) { 143 // See MIPS ARM Vol 3, Revision 2, Page 38 144 tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE)); | 137 if (FULL_SYSTEM) { 138 DPRINTF(MipsPRA, "Fault %s encountered.\n", name()); 139 setExceptionState(tc, code()); 140 tc->pcState(vect(tc)); |
145 } else { | 141 } else { |
146 tc->pcState(0xBFC00200); | 142 panic("Fault %s encountered.\n", name()); |
147 } 148} 149 150void | 143 } 144} 145 146void |
151TrapFault::invoke(ThreadContext *tc, StaticInstPtr inst) | 147ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst) |
152{ | 148{ |
153 DPRINTF(MipsPRA, "%s encountered.\n", name()); 154 setExceptionState(tc, 0xD); 155 156 tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE)); 157} 158 159void 160BreakpointFault::invoke(ThreadContext *tc, StaticInstPtr inst) 161{ 162 setExceptionState(tc, 0x9); 163 164 tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE)); 165} 166 167void 168AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst) 169{ 170 DPRINTF(MipsPRA, "%s encountered.\n", name()); 171 setExceptionState(tc, store ? 0x5 : 0x4); 172 tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr); 173 174 tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE)); 175} 176 177void 178TlbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst) 179{ 180 setTlbExceptionState(tc, store ? 0x3 : 0x2); 181 tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE)); 182} 183 184void 185TlbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst) 186{ 187 // Since handler depends on EXL bit, must check EXL bit before setting it!! 188 StatusReg status = tc->readMiscReg(MISCREG_STATUS); 189 190 setTlbExceptionState(tc, store ? 0x3 : 0x2); 191 192 // See MIPS ARM Vol 3, Revision 2, Page 38 193 if (status.exl == 1) { 194 tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE)); 195 } else { 196 tc->pcState(tc->readMiscReg(MISCREG_EBASE)); | 149 if (FULL_SYSTEM) { 150 DPRINTF(MipsPRA, "%s encountered.\n", name()); 151 /* All reset activity must be invoked from here */ 152 Addr handler = vect(tc); 153 tc->pcState(handler); 154 DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler); |
197 } | 155 } |
198} | |
199 | 156 |
200void 201TlbModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst) 202{ 203 setTlbExceptionState(tc, 0x1); 204 205 tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE)); 206} 207 208void 209SystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst) 210{ 211 DPRINTF(MipsPRA, "%s encountered.\n", name()); 212 setExceptionState(tc, 0x8); 213 214 tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE)); 215} 216 217void 218InterruptFault::invoke(ThreadContext *tc, StaticInstPtr inst) 219{ 220 DPRINTF(MipsPRA, "%s encountered.\n", name()); 221 setExceptionState(tc, 0x0A); 222 223 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); 224 if (cause.iv) { 225 // Offset 200 for release 2 226 tc->pcState(0x20 + vect() + tc->readMiscRegNoEffect(MISCREG_EBASE)); 227 } else { 228 //Ofset at 180 for release 1 229 tc->pcState(vect() + tc->readMiscRegNoEffect(MISCREG_EBASE)); 230 } 231} 232 233#endif // FULL_SYSTEM 234 235void 236ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst) 237{ 238#if FULL_SYSTEM 239 DPRINTF(MipsPRA, "%s encountered.\n", name()); 240 /* All reset activity must be invoked from here */ 241 tc->pcState(vect()); 242 DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC()); 243#endif 244 | |
245 // Set Coprocessor 1 (Floating Point) To Usable 246 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); 247 status.cu.cu1 = 1; 248 tc->setMiscReg(MISCREG_STATUS, status); 249} 250 251void | 157 // Set Coprocessor 1 (Floating Point) To Usable 158 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); 159 status.cu.cu1 = 1; 160 tc->setMiscReg(MISCREG_STATUS, status); 161} 162 163void |
252ReservedInstructionFault::invoke(ThreadContext *tc, StaticInstPtr inst) | 164SoftResetFault::invoke(ThreadContext *tc, StaticInstPtr inst) |
253{ | 165{ |
254#if FULL_SYSTEM 255 DPRINTF(MipsPRA, "%s encountered.\n", name()); 256 setExceptionState(tc, 0x0A); 257 tc->pcState(vect() + tc->readMiscRegNoEffect(MISCREG_EBASE)); 258#else 259 panic("%s encountered.\n", name()); 260#endif | 166 panic("Soft reset not implemented.\n"); |
261} 262 263void | 167} 168 169void |
264ThreadFault::invoke(ThreadContext *tc, StaticInstPtr inst) | 170NonMaskableInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst) |
265{ | 171{ |
266 DPRINTF(MipsPRA, "%s encountered.\n", name()); 267 panic("%s encountered.\n", name()); | 172 panic("Non maskable interrupt not implemented.\n"); |
268} 269 | 173} 174 |
270void 271DspStateDisabledFault::invoke(ThreadContext *tc, StaticInstPtr inst) 272{ 273 DPRINTF(MipsPRA, "%s encountered.\n", name()); 274 panic("%s encountered.\n", name()); 275} 276 277void 278CoprocessorUnusableFault::invoke(ThreadContext *tc, StaticInstPtr inst) 279{ 280#if FULL_SYSTEM 281 DPRINTF(MipsPRA, "%s encountered.\n", name()); 282 setExceptionState(tc, 0xb); 283 // The ID of the coprocessor causing the exception is stored in 284 // CoprocessorUnusableFault::coProcID 285 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 286 cause.ce = coProcID; 287 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 288 tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE)); 289#else 290 warn("%s (CP%d) encountered.\n", name(), coProcID); 291#endif 292} 293 | |
294} // namespace MipsISA 295 | 175} // namespace MipsISA 176 |