faults.cc (8574:16a168a366d8) faults.cc (8575:02332ce6d7da)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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86 { "Breakpoint", 0x0180 };
87
88template <> FaultVals MipsFault<TlbInvalidFault>::vals =
89 { "Invalid TLB Entry Exception", 0x0180 };
90
91template <> FaultVals MipsFault<TlbRefillFault>::vals =
92 { "TLB Refill Exception", 0x0180 };
93
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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86 { "Breakpoint", 0x0180 };
87
88template <> FaultVals MipsFault<TlbInvalidFault>::vals =
89 { "Invalid TLB Entry Exception", 0x0180 };
90
91template <> FaultVals MipsFault<TlbRefillFault>::vals =
92 { "TLB Refill Exception", 0x0180 };
93
94template <> FaultVals MipsFault<TLBModifiedFault>::vals =
94template <> FaultVals MipsFault<TlbModifiedFault>::vals =
95 { "TLB Modified Exception", 0x0180 };
96
97template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
98 { "DSP Disabled Fault", 0x001a };
99
100void
101MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
102{

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179 // Set new PC
180 Addr HandlerBase;
181 // Offset 0x180 - General Exception Vector
182 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
183 setHandlerPC(HandlerBase, tc);
184}
185
186void
95 { "TLB Modified Exception", 0x0180 };
96
97template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
98 { "DSP Disabled Fault", 0x001a };
99
100void
101MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
102{

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179 // Set new PC
180 Addr HandlerBase;
181 // Offset 0x180 - General Exception Vector
182 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
183 setHandlerPC(HandlerBase, tc);
184}
185
186void
187TlbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
187AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
188{
189 DPRINTF(MipsPRA, "%s encountered.\n", name());
188{
189 DPRINTF(MipsPRA, "%s encountered.\n", name());
190 setExceptionState(tc, store ? 0x3 : 0x2);
190 setExceptionState(tc, store ? 0x5 : 0x4);
191 tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
191
192
192 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
193 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
194 entryHi.asid = entryHiAsid;
195 entryHi.vpn2 = entryHiVPN2;
196 entryHi.vpn2x = entryHiVPN2X;
197 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
198
199 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
200 context.badVPN2 = contextBadVPN2;
201 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
202
203 // Set new PC
204 Addr HandlerBase;
205 // Offset 0x180 - General Exception Vector
206 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
207 setHandlerPC(HandlerBase, tc);
208}
209
210void
193 // Set new PC
194 Addr HandlerBase;
195 // Offset 0x180 - General Exception Vector
196 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
197 setHandlerPC(HandlerBase, tc);
198}
199
200void
211AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
201TlbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
212{
202{
213 DPRINTF(MipsPRA, "%s encountered.\n", name());
214 setExceptionState(tc, store ? 0x5 : 0x4);
215 tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
216
203 setTlbExceptionState(tc, store ? 0x3 : 0x2);
217 // Set new PC
218 Addr HandlerBase;
219 // Offset 0x180 - General Exception Vector
220 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
221 setHandlerPC(HandlerBase, tc);
222}
223
224void
225TlbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
226{
204 // Set new PC
205 Addr HandlerBase;
206 // Offset 0x180 - General Exception Vector
207 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
208 setHandlerPC(HandlerBase, tc);
209}
210
211void
212TlbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
213{
227 DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR);
228 setExceptionState(tc, store ? 0x3 : 0x2);
214 // Since handler depends on EXL bit, must check EXL bit before setting it!!
215 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
229
216
230 Addr HandlerBase;
231 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
232 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
233 entryHi.asid = entryHiAsid;
234 entryHi.vpn2 = entryHiVPN2;
235 entryHi.vpn2x = entryHiVPN2X;
236 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
237 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
238 context.badVPN2 = contextBadVPN2;
239 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
217 setTlbExceptionState(tc, store ? 0x3 : 0x2);
240
218
241 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
242 // Since handler depends on EXL bit, must check EXL bit before setting it!!
243 // See MIPS ARM Vol 3, Revision 2, Page 38
244 if (status.exl == 1) {
245 // Offset 0x180 - General Exception Vector
246 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
247 } else {
248 // Offset 0x000
249 HandlerBase = tc->readMiscReg(MISCREG_EBASE);
250 }
251 setHandlerPC(HandlerBase, tc);
252}
253
254void
219 // See MIPS ARM Vol 3, Revision 2, Page 38
220 if (status.exl == 1) {
221 // Offset 0x180 - General Exception Vector
222 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
223 } else {
224 // Offset 0x000
225 HandlerBase = tc->readMiscReg(MISCREG_EBASE);
226 }
227 setHandlerPC(HandlerBase, tc);
228}
229
230void
255TLBModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst)
231TlbModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst)
256{
232{
257 DPRINTF(MipsPRA, "%s encountered.\n", name());
258 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
259 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
260 entryHi.asid = entryHiAsid;
261 entryHi.vpn2 = entryHiVPN2;
262 entryHi.vpn2x = entryHiVPN2X;
263 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
233 setTlbExceptionState(tc, 0x1);
264
234
265 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
266 context.badVPN2 = contextBadVPN2;
267 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
268
269 // Set new PC
270 Addr HandlerBase;
271 // Offset 0x180 - General Exception Vector
272 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
235 // Set new PC
236 Addr HandlerBase;
237 // Offset 0x180 - General Exception Vector
238 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
273 setExceptionState(tc, 0x1);
274 setHandlerPC(HandlerBase, tc);
239 setHandlerPC(HandlerBase, tc);
275
276}
277
278void
279SystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst)
280{
281 DPRINTF(MipsPRA, "%s encountered.\n", name());
282 setExceptionState(tc, 0x8);
283

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241
242void
243SystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst)
244{
245 DPRINTF(MipsPRA, "%s encountered.\n", name());
246 setExceptionState(tc, 0x8);
247

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