faults.cc (8570:ea93f18eead8) faults.cc (8573:be51bef13962)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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80 { "interrupt", 0x0180 };
81
82template <> FaultVals MipsFault<TrapFault>::vals =
83 { "Trap", 0x0180 };
84
85template <> FaultVals MipsFault<BreakpointFault>::vals =
86 { "Breakpoint", 0x0180 };
87
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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80 { "interrupt", 0x0180 };
81
82template <> FaultVals MipsFault<TrapFault>::vals =
83 { "Trap", 0x0180 };
84
85template <> FaultVals MipsFault<BreakpointFault>::vals =
86 { "Breakpoint", 0x0180 };
87
88template <> FaultVals MipsFault<ItbInvalidFault>::vals =
89 { "Invalid TLB Entry Exception (I-Fetch/LW)", 0x0180 };
88template <> FaultVals MipsFault<TlbInvalidFault>::vals =
89 { "Invalid TLB Entry Exception", 0x0180 };
90
90
91template <> FaultVals MipsFault<ItbRefillFault>::vals =
92 { "TLB Refill Exception (I-Fetch/LW)", 0x0180 };
91template <> FaultVals MipsFault<TlbRefillFault>::vals =
92 { "TLB Refill Exception", 0x0180 };
93
93
94template <> FaultVals MipsFault<DtbInvalidFault>::vals =
95 { "Invalid TLB Entry Exception (Store)", 0x0180 };
96
97template <> FaultVals MipsFault<DtbRefillFault>::vals =
98 { "TLB Refill Exception (Store)", 0x0180 };
99
100template <> FaultVals MipsFault<TLBModifiedFault>::vals =
101 { "TLB Modified Exception", 0x0180 };
102
103template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
104 { "DSP Disabled Fault", 0x001a };
105
106#if FULL_SYSTEM
107void

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194 // Set new PC
195 Addr HandlerBase;
196 // Offset 0x180 - General Exception Vector
197 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
198 setHandlerPC(HandlerBase, tc);
199}
200
201void
94template <> FaultVals MipsFault<TLBModifiedFault>::vals =
95 { "TLB Modified Exception", 0x0180 };
96
97template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
98 { "DSP Disabled Fault", 0x001a };
99
100#if FULL_SYSTEM
101void

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188 // Set new PC
189 Addr HandlerBase;
190 // Offset 0x180 - General Exception Vector
191 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
192 setHandlerPC(HandlerBase, tc);
193}
194
195void
202DtbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
196TlbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
203{
204 DPRINTF(MipsPRA, "%s encountered.\n", name());
197{
198 DPRINTF(MipsPRA, "%s encountered.\n", name());
199 setExceptionState(tc, store ? 0x3 : 0x2);
205
206 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
207 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
208 entryHi.asid = entryHiAsid;
209 entryHi.vpn2 = entryHiVPN2;
210 entryHi.vpn2x = entryHiVPN2X;
211 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
212
213 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
214 context.badVPN2 = contextBadVPN2;
215 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
200
201 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
202 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
203 entryHi.asid = entryHiAsid;
204 entryHi.vpn2 = entryHiVPN2;
205 entryHi.vpn2x = entryHiVPN2X;
206 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
207
208 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
209 context.badVPN2 = contextBadVPN2;
210 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
216 setExceptionState(tc, 0x3);
217
211
218
219 // Set new PC
220 Addr HandlerBase;
221 // Offset 0x180 - General Exception Vector
222 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
223 setHandlerPC(HandlerBase, tc);
224}
225
226void

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233 // Set new PC
234 Addr HandlerBase;
235 // Offset 0x180 - General Exception Vector
236 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
237 setHandlerPC(HandlerBase, tc);
238}
239
240void
212 // Set new PC
213 Addr HandlerBase;
214 // Offset 0x180 - General Exception Vector
215 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
216 setHandlerPC(HandlerBase, tc);
217}
218
219void

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226 // Set new PC
227 Addr HandlerBase;
228 // Offset 0x180 - General Exception Vector
229 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
230 setHandlerPC(HandlerBase, tc);
231}
232
233void
241ItbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
234TlbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
242{
235{
243 DPRINTF(MipsPRA, "%s encountered.\n", name());
244 setExceptionState(tc, 0x2);
245 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
246 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
247 entryHi.asid = entryHiAsid;
248 entryHi.vpn2 = entryHiVPN2;
249 entryHi.vpn2x = entryHiVPN2X;
250 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
236 DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR);
237 setExceptionState(tc, store ? 0x3 : 0x2);
251
238
252 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
253 context.badVPN2 = contextBadVPN2;
254 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
255
256
257 // Set new PC
258 Addr HandlerBase;
239 Addr HandlerBase;
259 // Offset 0x180 - General Exception Vector
260 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
261 setHandlerPC(HandlerBase,tc);
262 DPRINTF(MipsPRA, "Exception Handler At: %x , EPC set to %x\n",
263 HandlerBase, tc->readMiscReg(MISCREG_EPC));
264}
265
266void
267ItbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
268{
269 DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR);
270 Addr HandlerBase;
271 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
272 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
273 entryHi.asid = entryHiAsid;
274 entryHi.vpn2 = entryHiVPN2;
275 entryHi.vpn2x = entryHiVPN2X;
276 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
277 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
278 context.badVPN2 = contextBadVPN2;

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283 // See MIPS ARM Vol 3, Revision 2, Page 38
284 if (status.exl == 1) {
285 // Offset 0x180 - General Exception Vector
286 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
287 } else {
288 // Offset 0x000
289 HandlerBase = tc->readMiscReg(MISCREG_EBASE);
290 }
240 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
241 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
242 entryHi.asid = entryHiAsid;
243 entryHi.vpn2 = entryHiVPN2;
244 entryHi.vpn2x = entryHiVPN2X;
245 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
246 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
247 context.badVPN2 = contextBadVPN2;

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252 // See MIPS ARM Vol 3, Revision 2, Page 38
253 if (status.exl == 1) {
254 // Offset 0x180 - General Exception Vector
255 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
256 } else {
257 // Offset 0x000
258 HandlerBase = tc->readMiscReg(MISCREG_EBASE);
259 }
291
292 setExceptionState(tc, 0x2);
293 setHandlerPC(HandlerBase, tc);
294}
295
296void
260 setHandlerPC(HandlerBase, tc);
261}
262
263void
297DtbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
298{
299 // Set new PC
300 DPRINTF(MipsPRA, "%s encountered.\n", name());
301 Addr HandlerBase;
302 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
303 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
304 entryHi.asid = entryHiAsid;
305 entryHi.vpn2 = entryHiVPN2;
306 entryHi.vpn2x = entryHiVPN2X;
307 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
308
309 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
310 context.badVPN2 = contextBadVPN2;
311 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
312
313 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
314 // Since handler depends on EXL bit, must check EXL bit before setting it!!
315 // See MIPS ARM Vol 3, Revision 2, Page 38
316 if (status.exl) {
317 // Offset 0x180 - General Exception Vector
318 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
319 } else {
320 // Offset 0x000
321 HandlerBase = tc->readMiscReg(MISCREG_EBASE);
322 }
323
324 setExceptionState(tc, 0x3);
325
326 setHandlerPC(HandlerBase, tc);
327}
328
329void
330TLBModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst)
331{
332 DPRINTF(MipsPRA, "%s encountered.\n", name());
333 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
334 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
335 entryHi.asid = entryHiAsid;
336 entryHi.vpn2 = entryHiVPN2;
337 entryHi.vpn2x = entryHiVPN2X;

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265{
266 DPRINTF(MipsPRA, "%s encountered.\n", name());
267 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
268 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
269 entryHi.asid = entryHiAsid;
270 entryHi.vpn2 = entryHiVPN2;
271 entryHi.vpn2x = entryHiVPN2X;

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