faults.cc (8568:83f728db3332) faults.cc (8570:ea93f18eead8)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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56 { "Reset Fault", 0xBFC00000};
57#else
58 { "Reset Fault", 0x001};
59#endif
60
61template <> FaultVals MipsFault<AddressErrorFault>::vals =
62 { "Address Error", 0x0180 };
63
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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56 { "Reset Fault", 0xBFC00000};
57#else
58 { "Reset Fault", 0x001};
59#endif
60
61template <> FaultVals MipsFault<AddressErrorFault>::vals =
62 { "Address Error", 0x0180 };
63
64template <> FaultVals MipsFault<StoreAddressErrorFault>::vals =
65 { "Store Address Error", 0x0180 };
66
67template <> FaultVals MipsFault<SystemCallFault>::vals =
68 { "Syscall", 0x0180 };
69
70template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
71 { "Coprocessor Unusable Fault", 0x180 };
72
73template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
74 { "Reserved Instruction Fault", 0x0180 };

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172 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
173 } else {
174 HandlerBase = 0xBFC00200;
175 }
176 setHandlerPC(HandlerBase, tc);
177}
178
179void
64template <> FaultVals MipsFault<SystemCallFault>::vals =
65 { "Syscall", 0x0180 };
66
67template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
68 { "Coprocessor Unusable Fault", 0x180 };
69
70template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
71 { "Reserved Instruction Fault", 0x0180 };

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169 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
170 } else {
171 HandlerBase = 0xBFC00200;
172 }
173 setHandlerPC(HandlerBase, tc);
174}
175
176void
180StoreAddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
181{
182 DPRINTF(MipsPRA, "%s encountered.\n", name());
183 setExceptionState(tc, 0x5);
184 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
185
186 // Set new PC
187 Addr HandlerBase;
188 // Offset 0x180 - General Exception Vector
189 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
190 setHandlerPC(HandlerBase, tc);
191}
192
193void
194TrapFault::invoke(ThreadContext *tc, StaticInstPtr inst)
195{
196 DPRINTF(MipsPRA, "%s encountered.\n", name());
197 setExceptionState(tc, 0xD);
198
199 // Set new PC
200 Addr HandlerBase;
201 // Offset 0x180 - General Exception Vector

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239 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
240 setHandlerPC(HandlerBase, tc);
241}
242
243void
244AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
245{
246 DPRINTF(MipsPRA, "%s encountered.\n", name());
177TrapFault::invoke(ThreadContext *tc, StaticInstPtr inst)
178{
179 DPRINTF(MipsPRA, "%s encountered.\n", name());
180 setExceptionState(tc, 0xD);
181
182 // Set new PC
183 Addr HandlerBase;
184 // Offset 0x180 - General Exception Vector

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222 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
223 setHandlerPC(HandlerBase, tc);
224}
225
226void
227AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
228{
229 DPRINTF(MipsPRA, "%s encountered.\n", name());
247 setExceptionState(tc, 0x4);
248 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
230 setExceptionState(tc, store ? 0x5 : 0x4);
231 tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
249
250 // Set new PC
251 Addr HandlerBase;
252 // Offset 0x180 - General Exception Vector
253 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
254 setHandlerPC(HandlerBase, tc);
255}
256

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233 // Set new PC
234 Addr HandlerBase;
235 // Offset 0x180 - General Exception Vector
236 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
237 setHandlerPC(HandlerBase, tc);
238}
239

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