faults.cc (8232:b28d06a175be) faults.cc (8566:812d279f7b51)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 32 unchanged lines hidden (view full) ---

41#if !FULL_SYSTEM
42#include "mem/page_table.hh"
43#include "sim/process.hh"
44#endif
45
46namespace MipsISA
47{
48
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 32 unchanged lines hidden (view full) ---

41#if !FULL_SYSTEM
42#include "mem/page_table.hh"
43#include "sim/process.hh"
44#endif
45
46namespace MipsISA
47{
48
49FaultName MachineCheckFault::_name = "Machine Check";
50FaultVect MachineCheckFault::_vect = 0x0401;
51FaultStat MachineCheckFault::_count;
49typedef MipsFaultBase::FaultVals FaultVals;
52
50
53FaultName AlignmentFault::_name = "Alignment";
54FaultVect AlignmentFault::_vect = 0x0301;
55FaultStat AlignmentFault::_count;
51template <> FaultVals MipsFault<MachineCheckFault>::vals =
52 { "Machine Check", 0x0401 };
56
53
57FaultName ResetFault::_name = "Reset Fault";
54template <> FaultVals MipsFault<AlignmentFault>::vals =
55 { "Alignment", 0x0301 };
56
57template <> FaultVals MipsFault<ResetFault>::vals =
58#if FULL_SYSTEM
58#if FULL_SYSTEM
59FaultVect ResetFault::_vect = 0xBFC00000;
59 { "Reset Fault", 0xBFC00000};
60#else
60#else
61FaultVect ResetFault::_vect = 0x001;
61 { "Reset Fault", 0x001};
62#endif
62#endif
63FaultStat ResetFault::_count;
64
63
65FaultName AddressErrorFault::_name = "Address Error";
66FaultVect AddressErrorFault::_vect = 0x0180;
67FaultStat AddressErrorFault::_count;
64template <> FaultVals MipsFault<AddressErrorFault>::vals =
65 { "Address Error", 0x0180 };
68
66
69FaultName StoreAddressErrorFault::_name = "Store Address Error";
70FaultVect StoreAddressErrorFault::_vect = 0x0180;
71FaultStat StoreAddressErrorFault::_count;
67template <> FaultVals MipsFault<StoreAddressErrorFault>::vals =
68 { "Store Address Error", 0x0180 };
72
69
70template <> FaultVals MipsFault<SystemCallFault>::vals =
71 { "Syscall", 0x0180 };
73
72
74FaultName SystemCallFault::_name = "Syscall";
75FaultVect SystemCallFault::_vect = 0x0180;
76FaultStat SystemCallFault::_count;
73template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
74 { "Coprocessor Unusable Fault", 0x180 };
77
75
78FaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable Fault";
79FaultVect CoprocessorUnusableFault::_vect = 0x180;
80FaultStat CoprocessorUnusableFault::_count;
76template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
77 { "Reserved Instruction Fault", 0x0180 };
81
78
82FaultName ReservedInstructionFault::_name = "Reserved Instruction Fault";
83FaultVect ReservedInstructionFault::_vect = 0x0180;
84FaultStat ReservedInstructionFault::_count;
79template <> FaultVals MipsFault<ThreadFault>::vals =
80 { "Thread Fault", 0x00F1 };
85
81
86FaultName ThreadFault::_name = "Thread Fault";
87FaultVect ThreadFault::_vect = 0x00F1;
88FaultStat ThreadFault::_count;
82template <> FaultVals MipsFault<ArithmeticFault>::vals =
83 { "Arithmetic Overflow Exception", 0x180 };
89
84
90FaultName ArithmeticFault::_name = "Arithmetic Overflow Exception";
91FaultVect ArithmeticFault::_vect = 0x180;
92FaultStat ArithmeticFault::_count;
85template <> FaultVals MipsFault<UnimplementedOpcodeFault>::vals =
86 { "opdec", 0x0481 };
93
87
94FaultName UnimplementedOpcodeFault::_name = "opdec";
95FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
96FaultStat UnimplementedOpcodeFault::_count;
88template <> FaultVals MipsFault<InterruptFault>::vals =
89 { "interrupt", 0x0180 };
97
90
98FaultName InterruptFault::_name = "interrupt";
99FaultVect InterruptFault::_vect = 0x0180;
100FaultStat InterruptFault::_count;
91template <> FaultVals MipsFault<TrapFault>::vals =
92 { "Trap", 0x0180 };
101
93
102FaultName TrapFault::_name = "Trap";
103FaultVect TrapFault::_vect = 0x0180;
104FaultStat TrapFault::_count;
94template <> FaultVals MipsFault<BreakpointFault>::vals =
95 { "Breakpoint", 0x0180 };
105
96
106FaultName BreakpointFault::_name = "Breakpoint";
107FaultVect BreakpointFault::_vect = 0x0180;
108FaultStat BreakpointFault::_count;
97template <> FaultVals MipsFault<ItbInvalidFault>::vals =
98 { "Invalid TLB Entry Exception (I-Fetch/LW)", 0x0180 };
109
99
110FaultName ItbInvalidFault::_name = "Invalid TLB Entry Exception (I-Fetch/LW)";
111FaultVect ItbInvalidFault::_vect = 0x0180;
112FaultStat ItbInvalidFault::_count;
100template <> FaultVals MipsFault<ItbPageFault>::vals =
101 { "itbmiss", 0x0181 };
113
102
114FaultName ItbPageFault::_name = "itbmiss";
115FaultVect ItbPageFault::_vect = 0x0181;
116FaultStat ItbPageFault::_count;
103template <> FaultVals MipsFault<ItbMissFault>::vals =
104 { "itbmiss", 0x0181 };
117
105
118FaultName ItbMissFault::_name = "itbmiss";
119FaultVect ItbMissFault::_vect = 0x0181;
120FaultStat ItbMissFault::_count;
106template <> FaultVals MipsFault<ItbAcvFault>::vals =
107 { "iaccvio", 0x0081 };
121
108
122FaultName ItbAcvFault::_name = "iaccvio";
123FaultVect ItbAcvFault::_vect = 0x0081;
124FaultStat ItbAcvFault::_count;
109template <> FaultVals MipsFault<ItbRefillFault>::vals =
110 { "TLB Refill Exception (I-Fetch/LW)", 0x0180 };
125
111
126FaultName ItbRefillFault::_name = "TLB Refill Exception (I-Fetch/LW)";
127FaultVect ItbRefillFault::_vect = 0x0180;
128FaultStat ItbRefillFault::_count;
112template <> FaultVals MipsFault<NDtbMissFault>::vals =
113 { "dtb_miss_single", 0x0201 };
129
114
130FaultName NDtbMissFault::_name = "dtb_miss_single";
131FaultVect NDtbMissFault::_vect = 0x0201;
132FaultStat NDtbMissFault::_count;
115template <> FaultVals MipsFault<PDtbMissFault>::vals =
116 { "dtb_miss_double", 0x0281 };
133
117
134FaultName PDtbMissFault::_name = "dtb_miss_double";
135FaultVect PDtbMissFault::_vect = 0x0281;
136FaultStat PDtbMissFault::_count;
118template <> FaultVals MipsFault<DtbPageFault>::vals =
119 { "dfault", 0x0381 };
137
120
138FaultName DtbPageFault::_name = "dfault";
139FaultVect DtbPageFault::_vect = 0x0381;
140FaultStat DtbPageFault::_count;
121template <> FaultVals MipsFault<DtbAcvFault>::vals =
122 { "dfault", 0x0381 };
141
123
142FaultName DtbAcvFault::_name = "dfault";
143FaultVect DtbAcvFault::_vect = 0x0381;
144FaultStat DtbAcvFault::_count;
124template <> FaultVals MipsFault<DtbInvalidFault>::vals =
125 { "Invalid TLB Entry Exception (Store)", 0x0180 };
145
126
146FaultName DtbInvalidFault::_name = "Invalid TLB Entry Exception (Store)";
147FaultVect DtbInvalidFault::_vect = 0x0180;
148FaultStat DtbInvalidFault::_count;
127template <> FaultVals MipsFault<DtbRefillFault>::vals =
128 { "TLB Refill Exception (Store)", 0x0180 };
149
129
150FaultName DtbRefillFault::_name = "TLB Refill Exception (Store)";
151FaultVect DtbRefillFault::_vect = 0x0180;
152FaultStat DtbRefillFault::_count;
130template <> FaultVals MipsFault<TLBModifiedFault>::vals =
131 { "TLB Modified Exception", 0x0180 };
153
132
154FaultName TLBModifiedFault::_name = "TLB Modified Exception";
155FaultVect TLBModifiedFault::_vect = 0x0180;
156FaultStat TLBModifiedFault::_count;
133template <> FaultVals MipsFault<FloatEnableFault>::vals =
134 { "float_enable_fault", 0x0581 };
157
135
158FaultName FloatEnableFault::_name = "float_enable_fault";
159FaultVect FloatEnableFault::_vect = 0x0581;
160FaultStat FloatEnableFault::_count;
136template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
137 { "Integer Overflow Fault", 0x0501 };
161
138
162FaultName IntegerOverflowFault::_name = "Integer Overflow Fault";
163FaultVect IntegerOverflowFault::_vect = 0x0501;
164FaultStat IntegerOverflowFault::_count;
139template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
140 { "DSP Disabled Fault", 0x001a };
165
141
166FaultName DspStateDisabledFault::_name = "DSP Disabled Fault";
167FaultVect DspStateDisabledFault::_vect = 0x001a;
168FaultStat DspStateDisabledFault::_count;
169
170#if FULL_SYSTEM
171void
142#if FULL_SYSTEM
143void
172MipsFault::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
144MipsFaultBase::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
173{
174 tc->setPC(HandlerBase);
175 tc->setNextPC(HandlerBase + sizeof(MachInst));
176 tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst));
177}
178
179void
145{
146 tc->setPC(HandlerBase);
147 tc->setNextPC(HandlerBase + sizeof(MachInst));
148 tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst));
149}
150
151void
180MipsFault::setExceptionState(ThreadContext *tc, uint8_t excCode)
152MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
181{
182 // modify SRS Ctl - Save CSS, put ESS into CSS
183 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
184 if (status.exl != 1 && status.bev != 1) {
185 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
186 SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
187 srsCtl.pss = srsCtl.css;
188 srsCtl.css = srsCtl.ess;

--- 349 unchanged lines hidden --- 		153{
154 // modify SRS Ctl - Save CSS, put ESS into CSS
155 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
156 if (status.exl != 1 && status.bev != 1) {
157 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
158 SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
159 srsCtl.pss = srsCtl.css;
160 srsCtl.css = srsCtl.ess;

--- 349 unchanged lines hidden ---