faults.cc (7676:92274350b953) faults.cc (7678:f19b6a3a8cec)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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212 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
213 cause.excCode = excCode;
214 cause.bd = bd;
215 cause.ce = 0;
216 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
217}
218
219void
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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212 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
213 cause.excCode = excCode;
214 cause.bd = bd;
215 cause.ce = 0;
216 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
217}
218
219void
220ArithmeticFault::invoke(ThreadContext *tc)
220ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
221{
222 DPRINTF(MipsPRA, "%s encountered.\n", name());
223 setExceptionState(tc, 0xC);
224
225 // Set new PC
226 Addr HandlerBase;
227 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
228 // Here, the handler is dependent on BEV, which is not modified by
229 // setExceptionState()
230 if (!status.bev) {
231 // See MIPS ARM Vol 3, Revision 2, Page 38
232 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
233 } else {
234 HandlerBase = 0xBFC00200;
235 }
236 setHandlerPC(HandlerBase, tc);
237}
238
239void
221{
222 DPRINTF(MipsPRA, "%s encountered.\n", name());
223 setExceptionState(tc, 0xC);
224
225 // Set new PC
226 Addr HandlerBase;
227 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
228 // Here, the handler is dependent on BEV, which is not modified by
229 // setExceptionState()
230 if (!status.bev) {
231 // See MIPS ARM Vol 3, Revision 2, Page 38
232 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
233 } else {
234 HandlerBase = 0xBFC00200;
235 }
236 setHandlerPC(HandlerBase, tc);
237}
238
239void
240StoreAddressErrorFault::invoke(ThreadContext *tc)
240StoreAddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
241{
242 DPRINTF(MipsPRA, "%s encountered.\n", name());
243 setExceptionState(tc, 0x5);
244 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
245
246 // Set new PC
247 Addr HandlerBase;
248 // Offset 0x180 - General Exception Vector
249 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
250 setHandlerPC(HandlerBase, tc);
251}
252
253void
241{
242 DPRINTF(MipsPRA, "%s encountered.\n", name());
243 setExceptionState(tc, 0x5);
244 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
245
246 // Set new PC
247 Addr HandlerBase;
248 // Offset 0x180 - General Exception Vector
249 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
250 setHandlerPC(HandlerBase, tc);
251}
252
253void
254TrapFault::invoke(ThreadContext *tc)
254TrapFault::invoke(ThreadContext *tc, StaticInstPtr inst)
255{
256 DPRINTF(MipsPRA, "%s encountered.\n", name());
257 setExceptionState(tc, 0xD);
258
259 // Set new PC
260 Addr HandlerBase;
261 // Offset 0x180 - General Exception Vector
262 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
263 setHandlerPC(HandlerBase, tc);
264}
265
266void
255{
256 DPRINTF(MipsPRA, "%s encountered.\n", name());
257 setExceptionState(tc, 0xD);
258
259 // Set new PC
260 Addr HandlerBase;
261 // Offset 0x180 - General Exception Vector
262 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
263 setHandlerPC(HandlerBase, tc);
264}
265
266void
267BreakpointFault::invoke(ThreadContext *tc)
267BreakpointFault::invoke(ThreadContext *tc, StaticInstPtr inst)
268{
269 setExceptionState(tc, 0x9);
270
271 // Set new PC
272 Addr HandlerBase;
273 // Offset 0x180 - General Exception Vector
274 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
275 setHandlerPC(HandlerBase, tc);
276}
277
278void
268{
269 setExceptionState(tc, 0x9);
270
271 // Set new PC
272 Addr HandlerBase;
273 // Offset 0x180 - General Exception Vector
274 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
275 setHandlerPC(HandlerBase, tc);
276}
277
278void
279DtbInvalidFault::invoke(ThreadContext *tc)
279DtbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
280{
281 DPRINTF(MipsPRA, "%s encountered.\n", name());
282
283 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
284 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
285 entryHi.asid = entryHiAsid;
286 entryHi.vpn2 = entryHiVPN2;
287 entryHi.vpn2x = entryHiVPN2X;

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296 // Set new PC
297 Addr HandlerBase;
298 // Offset 0x180 - General Exception Vector
299 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
300 setHandlerPC(HandlerBase, tc);
301}
302
303void
280{
281 DPRINTF(MipsPRA, "%s encountered.\n", name());
282
283 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
284 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
285 entryHi.asid = entryHiAsid;
286 entryHi.vpn2 = entryHiVPN2;
287 entryHi.vpn2x = entryHiVPN2X;

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296 // Set new PC
297 Addr HandlerBase;
298 // Offset 0x180 - General Exception Vector
299 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
300 setHandlerPC(HandlerBase, tc);
301}
302
303void
304AddressErrorFault::invoke(ThreadContext *tc)
304AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
305{
306 DPRINTF(MipsPRA, "%s encountered.\n", name());
307 setExceptionState(tc, 0x4);
308 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
309
310 // Set new PC
311 Addr HandlerBase;
312 // Offset 0x180 - General Exception Vector
313 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
314 setHandlerPC(HandlerBase, tc);
315}
316
317void
305{
306 DPRINTF(MipsPRA, "%s encountered.\n", name());
307 setExceptionState(tc, 0x4);
308 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
309
310 // Set new PC
311 Addr HandlerBase;
312 // Offset 0x180 - General Exception Vector
313 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
314 setHandlerPC(HandlerBase, tc);
315}
316
317void
318ItbInvalidFault::invoke(ThreadContext *tc)
318ItbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
319{
320 DPRINTF(MipsPRA, "%s encountered.\n", name());
321 setExceptionState(tc, 0x2);
322 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
323 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
324 entryHi.asid = entryHiAsid;
325 entryHi.vpn2 = entryHiVPN2;
326 entryHi.vpn2x = entryHiVPN2X;

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336 // Offset 0x180 - General Exception Vector
337 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
338 setHandlerPC(HandlerBase,tc);
339 DPRINTF(MipsPRA, "Exception Handler At: %x , EPC set to %x\n",
340 HandlerBase, tc->readMiscReg(MISCREG_EPC));
341}
342
343void
319{
320 DPRINTF(MipsPRA, "%s encountered.\n", name());
321 setExceptionState(tc, 0x2);
322 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
323 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
324 entryHi.asid = entryHiAsid;
325 entryHi.vpn2 = entryHiVPN2;
326 entryHi.vpn2x = entryHiVPN2X;

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336 // Offset 0x180 - General Exception Vector
337 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
338 setHandlerPC(HandlerBase,tc);
339 DPRINTF(MipsPRA, "Exception Handler At: %x , EPC set to %x\n",
340 HandlerBase, tc->readMiscReg(MISCREG_EPC));
341}
342
343void
344ItbRefillFault::invoke(ThreadContext *tc)
344ItbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
345{
346 DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR);
347 Addr HandlerBase;
348 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
349 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
350 entryHi.asid = entryHiAsid;
351 entryHi.vpn2 = entryHiVPN2;
352 entryHi.vpn2x = entryHiVPN2X;

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366 HandlerBase = tc->readMiscReg(MISCREG_EBASE);
367 }
368
369 setExceptionState(tc, 0x2);
370 setHandlerPC(HandlerBase, tc);
371}
372
373void
345{
346 DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR);
347 Addr HandlerBase;
348 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
349 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
350 entryHi.asid = entryHiAsid;
351 entryHi.vpn2 = entryHiVPN2;
352 entryHi.vpn2x = entryHiVPN2X;

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366 HandlerBase = tc->readMiscReg(MISCREG_EBASE);
367 }
368
369 setExceptionState(tc, 0x2);
370 setHandlerPC(HandlerBase, tc);
371}
372
373void
374DtbRefillFault::invoke(ThreadContext *tc)
374DtbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
375{
376 // Set new PC
377 DPRINTF(MipsPRA, "%s encountered.\n", name());
378 Addr HandlerBase;
379 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
380 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
381 entryHi.asid = entryHiAsid;
382 entryHi.vpn2 = entryHiVPN2;

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399 }
400
401 setExceptionState(tc, 0x3);
402
403 setHandlerPC(HandlerBase, tc);
404}
405
406void
375{
376 // Set new PC
377 DPRINTF(MipsPRA, "%s encountered.\n", name());
378 Addr HandlerBase;
379 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
380 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
381 entryHi.asid = entryHiAsid;
382 entryHi.vpn2 = entryHiVPN2;

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399 }
400
401 setExceptionState(tc, 0x3);
402
403 setHandlerPC(HandlerBase, tc);
404}
405
406void
407TLBModifiedFault::invoke(ThreadContext *tc)
407TLBModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst)
408{
409 DPRINTF(MipsPRA, "%s encountered.\n", name());
410 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
411 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
412 entryHi.asid = entryHiAsid;
413 entryHi.vpn2 = entryHiVPN2;
414 entryHi.vpn2x = entryHiVPN2X;
415 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);

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423 // Offset 0x180 - General Exception Vector
424 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
425 setExceptionState(tc, 0x1);
426 setHandlerPC(HandlerBase, tc);
427
428}
429
430void
408{
409 DPRINTF(MipsPRA, "%s encountered.\n", name());
410 tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
411 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
412 entryHi.asid = entryHiAsid;
413 entryHi.vpn2 = entryHiVPN2;
414 entryHi.vpn2x = entryHiVPN2X;
415 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);

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423 // Offset 0x180 - General Exception Vector
424 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
425 setExceptionState(tc, 0x1);
426 setHandlerPC(HandlerBase, tc);
427
428}
429
430void
431SystemCallFault::invoke(ThreadContext *tc)
431SystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst)
432{
433 DPRINTF(MipsPRA, "%s encountered.\n", name());
434 setExceptionState(tc, 0x8);
435
436 // Set new PC
437 Addr HandlerBase;
438 // Offset 0x180 - General Exception Vector
439 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
440 setHandlerPC(HandlerBase, tc);
441}
442
443void
432{
433 DPRINTF(MipsPRA, "%s encountered.\n", name());
434 setExceptionState(tc, 0x8);
435
436 // Set new PC
437 Addr HandlerBase;
438 // Offset 0x180 - General Exception Vector
439 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
440 setHandlerPC(HandlerBase, tc);
441}
442
443void
444InterruptFault::invoke(ThreadContext *tc)
444InterruptFault::invoke(ThreadContext *tc, StaticInstPtr inst)
445{
446#if FULL_SYSTEM
447 DPRINTF(MipsPRA, "%s encountered.\n", name());
448 setExceptionState(tc, 0x0A);
449 Addr HandlerBase;
450
451 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
452 if (cause.iv) {

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459
460 setHandlerPC(HandlerBase, tc);
461#endif
462}
463
464#endif // FULL_SYSTEM
465
466void
445{
446#if FULL_SYSTEM
447 DPRINTF(MipsPRA, "%s encountered.\n", name());
448 setExceptionState(tc, 0x0A);
449 Addr HandlerBase;
450
451 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
452 if (cause.iv) {

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459
460 setHandlerPC(HandlerBase, tc);
461#endif
462}
463
464#endif // FULL_SYSTEM
465
466void
467ResetFault::invoke(ThreadContext *tc)
467ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
468{
469#if FULL_SYSTEM
470 DPRINTF(MipsPRA, "%s encountered.\n", name());
471 /* All reset activity must be invoked from here */
472 tc->setPC(vect());
473 tc->setNextPC(vect() + sizeof(MachInst));
474 tc->setNextNPC(vect() + sizeof(MachInst) + sizeof(MachInst));
475 DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC());
476#endif
477
478 // Set Coprocessor 1 (Floating Point) To Usable
479 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
480 status.cu.cu1 = 1;
481 tc->setMiscReg(MISCREG_STATUS, status);
482}
483
484void
468{
469#if FULL_SYSTEM
470 DPRINTF(MipsPRA, "%s encountered.\n", name());
471 /* All reset activity must be invoked from here */
472 tc->setPC(vect());
473 tc->setNextPC(vect() + sizeof(MachInst));
474 tc->setNextNPC(vect() + sizeof(MachInst) + sizeof(MachInst));
475 DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC());
476#endif
477
478 // Set Coprocessor 1 (Floating Point) To Usable
479 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
480 status.cu.cu1 = 1;
481 tc->setMiscReg(MISCREG_STATUS, status);
482}
483
484void
485ReservedInstructionFault::invoke(ThreadContext *tc)
485ReservedInstructionFault::invoke(ThreadContext *tc, StaticInstPtr inst)
486{
487#if FULL_SYSTEM
488 DPRINTF(MipsPRA, "%s encountered.\n", name());
489 setExceptionState(tc, 0x0A);
490 Addr HandlerBase;
491 // Offset 0x180 - General Exception Vector
492 HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE);
493 setHandlerPC(HandlerBase, tc);
494#else
495 panic("%s encountered.\n", name());
496#endif
497}
498
499void
486{
487#if FULL_SYSTEM
488 DPRINTF(MipsPRA, "%s encountered.\n", name());
489 setExceptionState(tc, 0x0A);
490 Addr HandlerBase;
491 // Offset 0x180 - General Exception Vector
492 HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE);
493 setHandlerPC(HandlerBase, tc);
494#else
495 panic("%s encountered.\n", name());
496#endif
497}
498
499void
500ThreadFault::invoke(ThreadContext *tc)
500ThreadFault::invoke(ThreadContext *tc, StaticInstPtr inst)
501{
502 DPRINTF(MipsPRA, "%s encountered.\n", name());
503 panic("%s encountered.\n", name());
504}
505
506void
501{
502 DPRINTF(MipsPRA, "%s encountered.\n", name());
503 panic("%s encountered.\n", name());
504}
505
506void
507DspStateDisabledFault::invoke(ThreadContext *tc)
507DspStateDisabledFault::invoke(ThreadContext *tc, StaticInstPtr inst)
508{
509 DPRINTF(MipsPRA, "%s encountered.\n", name());
510 panic("%s encountered.\n", name());
511}
512
513void
508{
509 DPRINTF(MipsPRA, "%s encountered.\n", name());
510 panic("%s encountered.\n", name());
511}
512
513void
514CoprocessorUnusableFault::invoke(ThreadContext *tc)
514CoprocessorUnusableFault::invoke(ThreadContext *tc, StaticInstPtr inst)
515{
516#if FULL_SYSTEM
517 DPRINTF(MipsPRA, "%s encountered.\n", name());
518 setExceptionState(tc, 0xb);
519 // The ID of the coprocessor causing the exception is stored in
520 // CoprocessorUnusableFault::coProcID
521 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
522 cause.ce = coProcID;

--- 14 unchanged lines hidden --- 		515{
516#if FULL_SYSTEM
517 DPRINTF(MipsPRA, "%s encountered.\n", name());
518 setExceptionState(tc, 0xb);
519 // The ID of the coprocessor causing the exception is stored in
520 // CoprocessorUnusableFault::coProcID
521 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
522 cause.ce = coProcID;

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