faults.cc (6378:4a2ff62c3b4f) faults.cc (6379:75d4aaf7dd54)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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170MipsFault::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
171{
172 tc->setPC(HandlerBase);
173 tc->setNextPC(HandlerBase + sizeof(MachInst));
174 tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst));
175}
176
177void
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 161 unchanged lines hidden (view full) ---

170MipsFault::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
171{
172 tc->setPC(HandlerBase);
173 tc->setNextPC(HandlerBase + sizeof(MachInst));
174 tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst));
175}
176
177void
178MipsFault::setExceptionState(ThreadContext *tc, uint8_t ExcCode)
178MipsFault::setExceptionState(ThreadContext *tc, uint8_t excCode)
179{
180 // modify SRS Ctl - Save CSS, put ESS into CSS
179{
180 // modify SRS Ctl - Save CSS, put ESS into CSS
181 MiscReg stat = tc->readMiscReg(MipsISA::Status);
182 if (bits(stat, Status_EXL) != 1 && bits(stat, Status_BEV) != 1) {
181 StatusReg status = tc->readMiscReg(Status);
182 if (status.exl != 1 && status.bev != 1) {
183 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
183 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
184 MiscReg srs = tc->readMiscReg(MipsISA::SRSCtl);
185 uint8_t CSS, ESS;
186 CSS = bits(srs, SRSCtl_CSS_HI, SRSCtl_CSS_LO);
187 ESS = bits(srs, SRSCtl_ESS_HI, SRSCtl_ESS_LO);
188 // Move CSS to PSS
189 replaceBits(srs, SRSCtl_PSS_HI, SRSCtl_PSS_LO, CSS);
190 // Move ESS to CSS
191 replaceBits(srs, SRSCtl_CSS_HI, SRSCtl_CSS_LO, ESS);
192 tc->setMiscRegNoEffect(MipsISA::SRSCtl, srs);
184 SRSCtlReg srsCtl = tc->readMiscReg(SRSCtl);
185 srsCtl.pss = srsCtl.css;
186 srsCtl.css = srsCtl.ess;
187 tc->setMiscRegNoEffect(SRSCtl, srsCtl);
193 }
194
195 // set EXL bit (don't care if it is already set!)
188 }
189
190 // set EXL bit (don't care if it is already set!)
196 replaceBits(stat, Status_EXL_HI, Status_EXL_LO, 1);
197 tc->setMiscRegNoEffect(MipsISA::Status, stat);
191 status.exl = 1;
192 tc->setMiscRegNoEffect(Status, status);
198
199 // write EPC
200 // CHECK ME or FIXME or FIX ME or POSSIBLE HACK
201 // Check to see if the exception occurred in the branch delay slot
202 DPRINTF(MipsPRA, "PC: %x, NextPC: %x, NNPC: %x\n",
203 tc->readPC(), tc->readNextPC(), tc->readNextNPC());
193
194 // write EPC
195 // CHECK ME or FIXME or FIX ME or POSSIBLE HACK
196 // Check to see if the exception occurred in the branch delay slot
197 DPRINTF(MipsPRA, "PC: %x, NextPC: %x, NNPC: %x\n",
198 tc->readPC(), tc->readNextPC(), tc->readNextNPC());
204 int C_BD = 0;
199 int bd = 0;
205 if (tc->readPC() + sizeof(MachInst) != tc->readNextPC()) {
200 if (tc->readPC() + sizeof(MachInst) != tc->readNextPC()) {
206 tc->setMiscRegNoEffect(MipsISA::EPC, tc->readPC() - sizeof(MachInst));
201 tc->setMiscRegNoEffect(EPC, tc->readPC() - sizeof(MachInst));
207 // In the branch delay slot? set CAUSE_31
202 // In the branch delay slot? set CAUSE_31
208 C_BD = 1;
203 bd = 1;
209 } else {
204 } else {
210 tc->setMiscRegNoEffect(MipsISA::EPC, tc->readPC());
205 tc->setMiscRegNoEffect(EPC, tc->readPC());
211 // In the branch delay slot? reset CAUSE_31
206 // In the branch delay slot? reset CAUSE_31
212 C_BD = 0;
207 bd = 0;
213 }
214
215 // Set Cause_EXCCODE field
208 }
209
210 // Set Cause_EXCCODE field
216 MiscReg cause = tc->readMiscReg(MipsISA::Cause);
217 replaceBits(cause, Cause_EXCCODE_HI, Cause_EXCCODE_LO, ExcCode);
218 replaceBits(cause, Cause_BD_HI, Cause_BD_LO,C_BD);
219 replaceBits(cause, Cause_CE_HI, Cause_CE_LO,0);
220 tc->setMiscRegNoEffect(MipsISA::Cause, cause);
211 CauseReg cause = tc->readMiscReg(Cause);
212 cause.excCode = excCode;
213 cause.bd = bd;
214 cause.ce = 0;
215 tc->setMiscRegNoEffect(Cause, cause);
221}
222
223void
224ArithmeticFault::invoke(ThreadContext *tc)
225{
226 DPRINTF(MipsPRA, "%s encountered.\n", name());
227 setExceptionState(tc, 0xC);
228
229 // Set new PC
230 Addr HandlerBase;
216}
217
218void
219ArithmeticFault::invoke(ThreadContext *tc)
220{
221 DPRINTF(MipsPRA, "%s encountered.\n", name());
222 setExceptionState(tc, 0xC);
223
224 // Set new PC
225 Addr HandlerBase;
231 MiscReg stat = tc->readMiscReg(MipsISA::Status);
226 StatusReg status = tc->readMiscReg(Status);
232 // Here, the handler is dependent on BEV, which is not modified by
233 // setExceptionState()
227 // Here, the handler is dependent on BEV, which is not modified by
228 // setExceptionState()
234 if (bits(stat, Status_BEV) == 0 ) {
229 if (!status.bev) {
235 // See MIPS ARM Vol 3, Revision 2, Page 38
230 // See MIPS ARM Vol 3, Revision 2, Page 38
236 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
231 HandlerBase = vect() + tc->readMiscReg(EBase);
237 } else {
238 HandlerBase = 0xBFC00200;
239 }
240 setHandlerPC(HandlerBase, tc);
241}
242
243void
244StoreAddressErrorFault::invoke(ThreadContext *tc)
245{
246 DPRINTF(MipsPRA, "%s encountered.\n", name());
247 setExceptionState(tc, 0x5);
232 } else {
233 HandlerBase = 0xBFC00200;
234 }
235 setHandlerPC(HandlerBase, tc);
236}
237
238void
239StoreAddressErrorFault::invoke(ThreadContext *tc)
240{
241 DPRINTF(MipsPRA, "%s encountered.\n", name());
242 setExceptionState(tc, 0x5);
248 tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
243 tc->setMiscRegNoEffect(BadVAddr, badVAddr);
249
250 // Set new PC
251 Addr HandlerBase;
252 // Offset 0x180 - General Exception Vector
244
245 // Set new PC
246 Addr HandlerBase;
247 // Offset 0x180 - General Exception Vector
253 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
248 HandlerBase = vect() + tc->readMiscReg(EBase);
254 setHandlerPC(HandlerBase, tc);
255}
256
257void
258TrapFault::invoke(ThreadContext *tc)
259{
260 DPRINTF(MipsPRA, "%s encountered.\n", name());
261 setExceptionState(tc, 0xD);
262
263 // Set new PC
264 Addr HandlerBase;
265 // Offset 0x180 - General Exception Vector
249 setHandlerPC(HandlerBase, tc);
250}
251
252void
253TrapFault::invoke(ThreadContext *tc)
254{
255 DPRINTF(MipsPRA, "%s encountered.\n", name());
256 setExceptionState(tc, 0xD);
257
258 // Set new PC
259 Addr HandlerBase;
260 // Offset 0x180 - General Exception Vector
266 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
261 HandlerBase = vect() + tc->readMiscReg(EBase);
267 setHandlerPC(HandlerBase, tc);
268}
269
270void
271BreakpointFault::invoke(ThreadContext *tc)
272{
273 setExceptionState(tc, 0x9);
274
275 // Set new PC
276 Addr HandlerBase;
277 // Offset 0x180 - General Exception Vector
262 setHandlerPC(HandlerBase, tc);
263}
264
265void
266BreakpointFault::invoke(ThreadContext *tc)
267{
268 setExceptionState(tc, 0x9);
269
270 // Set new PC
271 Addr HandlerBase;
272 // Offset 0x180 - General Exception Vector
278 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
273 HandlerBase = vect() + tc->readMiscReg(EBase);
279 setHandlerPC(HandlerBase, tc);
280}
281
282void
283DtbInvalidFault::invoke(ThreadContext *tc)
284{
285 DPRINTF(MipsPRA, "%s encountered.\n", name());
286
274 setHandlerPC(HandlerBase, tc);
275}
276
277void
278DtbInvalidFault::invoke(ThreadContext *tc)
279{
280 DPRINTF(MipsPRA, "%s encountered.\n", name());
281
287 tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
288 MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
289 replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
290 replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
291 replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
292 tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
293 MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
294 replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
295 tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
282 tc->setMiscRegNoEffect(BadVAddr, badVAddr);
283 EntryHiReg entryHi = tc->readMiscReg(EntryHi);
284 entryHi.asid = entryHiAsid;
285 entryHi.vpn2 = entryHiVPN2;
286 entryHi.vpn2x = entryHiVPN2X;
287 tc->setMiscRegNoEffect(EntryHi, entryHi);
288
289 ContextReg context = tc->readMiscReg(Context);
290 context.badVPN2 = contextBadVPN2;
291 tc->setMiscRegNoEffect(Context, context);
296 setExceptionState(tc, 0x3);
297
298
299 // Set new PC
300 Addr HandlerBase;
301 // Offset 0x180 - General Exception Vector
292 setExceptionState(tc, 0x3);
293
294
295 // Set new PC
296 Addr HandlerBase;
297 // Offset 0x180 - General Exception Vector
302 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
303 setHandlerPC(HandlerBase,tc);
298 HandlerBase = vect() + tc->readMiscReg(EBase);
299 setHandlerPC(HandlerBase, tc);
304}
305
306void
307AddressErrorFault::invoke(ThreadContext *tc)
308{
309 DPRINTF(MipsPRA, "%s encountered.\n", name());
310 setExceptionState(tc, 0x4);
300}
301
302void
303AddressErrorFault::invoke(ThreadContext *tc)
304{
305 DPRINTF(MipsPRA, "%s encountered.\n", name());
306 setExceptionState(tc, 0x4);
311 tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
307 tc->setMiscRegNoEffect(BadVAddr, badVAddr);
312
313 // Set new PC
314 Addr HandlerBase;
315 // Offset 0x180 - General Exception Vector
308
309 // Set new PC
310 Addr HandlerBase;
311 // Offset 0x180 - General Exception Vector
316 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
312 HandlerBase = vect() + tc->readMiscReg(EBase);
317 setHandlerPC(HandlerBase, tc);
318}
319
320void
321ItbInvalidFault::invoke(ThreadContext *tc)
322{
323 DPRINTF(MipsPRA, "%s encountered.\n", name());
324 setExceptionState(tc, 0x2);
313 setHandlerPC(HandlerBase, tc);
314}
315
316void
317ItbInvalidFault::invoke(ThreadContext *tc)
318{
319 DPRINTF(MipsPRA, "%s encountered.\n", name());
320 setExceptionState(tc, 0x2);
325 tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
326 MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
327 replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
328 replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
329 replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
330 tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
331 MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
332 replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
333 tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
321 tc->setMiscRegNoEffect(BadVAddr, badVAddr);
322 EntryHiReg entryHi = tc->readMiscReg(EntryHi);
323 entryHi.asid = entryHiAsid;
324 entryHi.vpn2 = entryHiVPN2;
325 entryHi.vpn2x = entryHiVPN2X;
326 tc->setMiscRegNoEffect(EntryHi, entryHi);
334
327
328 ContextReg context = tc->readMiscReg(Context);
329 context.badVPN2 = contextBadVPN2;
330 tc->setMiscRegNoEffect(Context, context);
335
331
332
336 // Set new PC
337 Addr HandlerBase;
338 // Offset 0x180 - General Exception Vector
333 // Set new PC
334 Addr HandlerBase;
335 // Offset 0x180 - General Exception Vector
339 HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase);
336 HandlerBase = vect() + tc->readMiscReg(EBase);
340 setHandlerPC(HandlerBase,tc);
337 setHandlerPC(HandlerBase,tc);
341 DPRINTF(MipsPRA,"Exception Handler At: %x , EPC set to %x\n",
342 HandlerBase, tc->readMiscReg(MipsISA::EPC));
338 DPRINTF(MipsPRA, "Exception Handler At: %x , EPC set to %x\n",
339 HandlerBase, tc->readMiscReg(EPC));
343}
344
345void
346ItbRefillFault::invoke(ThreadContext *tc)
347{
340}
341
342void
343ItbRefillFault::invoke(ThreadContext *tc)
344{
348 DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), BadVAddr);
345 DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), badVAddr);
349 Addr HandlerBase;
346 Addr HandlerBase;
350 tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
351 MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
352 replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
353 replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
354 replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
355 tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
356 MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
357 replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
358 tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
347 tc->setMiscRegNoEffect(BadVAddr, badVAddr);
348 EntryHiReg entryHi = tc->readMiscReg(EntryHi);
349 entryHi.asid = entryHiAsid;
350 entryHi.vpn2 = entryHiVPN2;
351 entryHi.vpn2x = entryHiVPN2X;
352 tc->setMiscRegNoEffect(EntryHi, entryHi);
353 ContextReg context = tc->readMiscReg(Context);
354 context.badVPN2 = contextBadVPN2;
355 tc->setMiscRegNoEffect(Context, context);
359
356
360 MiscReg stat = tc->readMiscReg(MipsISA::Status);
357 StatusReg status = tc->readMiscReg(Status);
361 // Since handler depends on EXL bit, must check EXL bit before setting it!!
362 // See MIPS ARM Vol 3, Revision 2, Page 38
358 // Since handler depends on EXL bit, must check EXL bit before setting it!!
359 // See MIPS ARM Vol 3, Revision 2, Page 38
363 if (bits(stat, Status_EXL) == 1) {
360 if (status.exl == 1) {
364 // Offset 0x180 - General Exception Vector
361 // Offset 0x180 - General Exception Vector
365 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
362 HandlerBase = vect() + tc->readMiscReg(EBase);
366 } else {
367 // Offset 0x000
363 } else {
364 // Offset 0x000
368 HandlerBase = tc->readMiscReg(MipsISA::EBase);
365 HandlerBase = tc->readMiscReg(EBase);
369 }
370
371 setExceptionState(tc, 0x2);
372 setHandlerPC(HandlerBase, tc);
373}
374
375void
376DtbRefillFault::invoke(ThreadContext *tc)
377{
378 // Set new PC
379 DPRINTF(MipsPRA, "%s encountered.\n", name());
380 Addr HandlerBase;
366 }
367
368 setExceptionState(tc, 0x2);
369 setHandlerPC(HandlerBase, tc);
370}
371
372void
373DtbRefillFault::invoke(ThreadContext *tc)
374{
375 // Set new PC
376 DPRINTF(MipsPRA, "%s encountered.\n", name());
377 Addr HandlerBase;
381 tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
382 MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
383 replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
384 replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
385 replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
386 tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
387 MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
388 replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
389 tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
378 tc->setMiscRegNoEffect(BadVAddr, badVAddr);
379 EntryHiReg entryHi = tc->readMiscReg(EntryHi);
380 entryHi.asid = entryHiAsid;
381 entryHi.vpn2 = entryHiVPN2;
382 entryHi.vpn2x = entryHiVPN2X;
383 tc->setMiscRegNoEffect(EntryHi, entryHi);
390
384
391 MiscReg stat = tc->readMiscReg(MipsISA::Status);
385 ContextReg context = tc->readMiscReg(Context);
386 context.badVPN2 = contextBadVPN2;
387 tc->setMiscRegNoEffect(Context, context);
388
389 StatusReg status = tc->readMiscReg(Status);
392 // Since handler depends on EXL bit, must check EXL bit before setting it!!
393 // See MIPS ARM Vol 3, Revision 2, Page 38
390 // Since handler depends on EXL bit, must check EXL bit before setting it!!
391 // See MIPS ARM Vol 3, Revision 2, Page 38
394 if(bits(stat, Status_EXL) == 1) {
392 if (status.exl) {
395 // Offset 0x180 - General Exception Vector
393 // Offset 0x180 - General Exception Vector
396 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
394 HandlerBase = vect() + tc->readMiscReg(EBase);
397 } else {
398 // Offset 0x000
395 } else {
396 // Offset 0x000
399 HandlerBase = tc->readMiscReg(MipsISA::EBase);
397 HandlerBase = tc->readMiscReg(EBase);
400 }
401
402 setExceptionState(tc, 0x3);
403
404 setHandlerPC(HandlerBase, tc);
405}
406
407void
408TLBModifiedFault::invoke(ThreadContext *tc)
409{
410 DPRINTF(MipsPRA, "%s encountered.\n", name());
398 }
399
400 setExceptionState(tc, 0x3);
401
402 setHandlerPC(HandlerBase, tc);
403}
404
405void
406TLBModifiedFault::invoke(ThreadContext *tc)
407{
408 DPRINTF(MipsPRA, "%s encountered.\n", name());
411 tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
412 MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
413 replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
414 replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
415 replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
416 tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
417 MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
418 replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
419 tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
409 tc->setMiscRegNoEffect(BadVAddr, badVAddr);
410 EntryHiReg entryHi = tc->readMiscReg(EntryHi);
411 entryHi.asid = entryHiAsid;
412 entryHi.vpn2 = entryHiVPN2;
413 entryHi.vpn2x = entryHiVPN2X;
414 tc->setMiscRegNoEffect(EntryHi, entryHi);
420
415
416 ContextReg context = tc->readMiscReg(Context);
417 context.badVPN2 = contextBadVPN2;
418 tc->setMiscRegNoEffect(Context, context);
419
421 // Set new PC
422 Addr HandlerBase;
423 // Offset 0x180 - General Exception Vector
420 // Set new PC
421 Addr HandlerBase;
422 // Offset 0x180 - General Exception Vector
424 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
423 HandlerBase = vect() + tc->readMiscReg(EBase);
425 setExceptionState(tc, 0x1);
426 setHandlerPC(HandlerBase, tc);
427
428}
429
430void
431SystemCallFault::invoke(ThreadContext *tc)
432{
433 DPRINTF(MipsPRA, "%s encountered.\n", name());
434 setExceptionState(tc, 0x8);
435
436 // Set new PC
437 Addr HandlerBase;
438 // Offset 0x180 - General Exception Vector
424 setExceptionState(tc, 0x1);
425 setHandlerPC(HandlerBase, tc);
426
427}
428
429void
430SystemCallFault::invoke(ThreadContext *tc)
431{
432 DPRINTF(MipsPRA, "%s encountered.\n", name());
433 setExceptionState(tc, 0x8);
434
435 // Set new PC
436 Addr HandlerBase;
437 // Offset 0x180 - General Exception Vector
439 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
438 HandlerBase = vect() + tc->readMiscReg(EBase);
440 setHandlerPC(HandlerBase, tc);
441}
442
443void
444InterruptFault::invoke(ThreadContext *tc)
445{
446#if FULL_SYSTEM
447 DPRINTF(MipsPRA, "%s encountered.\n", name());
448 setExceptionState(tc, 0x0A);
449 Addr HandlerBase;
450
439 setHandlerPC(HandlerBase, tc);
440}
441
442void
443InterruptFault::invoke(ThreadContext *tc)
444{
445#if FULL_SYSTEM
446 DPRINTF(MipsPRA, "%s encountered.\n", name());
447 setExceptionState(tc, 0x0A);
448 Addr HandlerBase;
449
451 uint8_t IV = bits(tc->readMiscRegNoEffect(MipsISA::Cause), Cause_IV);
452 if (IV) {
450 CauseReg cause = tc->readMiscRegNoEffect(Cause);
451 if (cause.iv) {
453 // Offset 200 for release 2
452 // Offset 200 for release 2
454 HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
453 HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(EBase);
455 } else {
456 //Ofset at 180 for release 1
454 } else {
455 //Ofset at 180 for release 1
457 HandlerBase = vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
456 HandlerBase = vect() + tc->readMiscRegNoEffect(EBase);
458 }
459
460 setHandlerPC(HandlerBase, tc);
461#endif
462}
463
464#endif // FULL_SYSTEM
465
466void
467ResetFault::invoke(ThreadContext *tc)
468{
469#if FULL_SYSTEM
470 DPRINTF(MipsPRA, "%s encountered.\n", name());
471 /* All reset activity must be invoked from here */
472 tc->setPC(vect());
473 tc->setNextPC(vect() + sizeof(MachInst));
474 tc->setNextNPC(vect() + sizeof(MachInst) + sizeof(MachInst));
457 }
458
459 setHandlerPC(HandlerBase, tc);
460#endif
461}
462
463#endif // FULL_SYSTEM
464
465void
466ResetFault::invoke(ThreadContext *tc)
467{
468#if FULL_SYSTEM
469 DPRINTF(MipsPRA, "%s encountered.\n", name());
470 /* All reset activity must be invoked from here */
471 tc->setPC(vect());
472 tc->setNextPC(vect() + sizeof(MachInst));
473 tc->setNextNPC(vect() + sizeof(MachInst) + sizeof(MachInst));
475 DPRINTF(MipsPRA, "(%x) - ResetFault::invoke : PC set to %x",
476 (unsigned)tc, (unsigned)tc->readPC());
474 DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC());
477#endif
478
479 // Set Coprocessor 1 (Floating Point) To Usable
475#endif
476
477 // Set Coprocessor 1 (Floating Point) To Usable
480 tc->setMiscReg(MipsISA::Status, MipsISA::Status | 0x20000000);
478 StatusReg status = tc->readMiscRegNoEffect(Status);
479 status.cu.cu1 = 1;
480 tc->setMiscReg(Status, status);
481}
482
483void
484ReservedInstructionFault::invoke(ThreadContext *tc)
485{
486#if FULL_SYSTEM
487 DPRINTF(MipsPRA, "%s encountered.\n", name());
488 setExceptionState(tc, 0x0A);
489 Addr HandlerBase;
490 // Offset 0x180 - General Exception Vector
481}
482
483void
484ReservedInstructionFault::invoke(ThreadContext *tc)
485{
486#if FULL_SYSTEM
487 DPRINTF(MipsPRA, "%s encountered.\n", name());
488 setExceptionState(tc, 0x0A);
489 Addr HandlerBase;
490 // Offset 0x180 - General Exception Vector
491 HandlerBase = vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
491 HandlerBase = vect() + tc->readMiscRegNoEffect(EBase);
492 setHandlerPC(HandlerBase, tc);
493#else
494 panic("%s encountered.\n", name());
495#endif
496}
497
498void
499ThreadFault::invoke(ThreadContext *tc)

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512void
513CoprocessorUnusableFault::invoke(ThreadContext *tc)
514{
515#if FULL_SYSTEM
516 DPRINTF(MipsPRA, "%s encountered.\n", name());
517 setExceptionState(tc, 0xb);
518 // The ID of the coprocessor causing the exception is stored in
519 // CoprocessorUnusableFault::coProcID
492 setHandlerPC(HandlerBase, tc);
493#else
494 panic("%s encountered.\n", name());
495#endif
496}
497
498void
499ThreadFault::invoke(ThreadContext *tc)

--- 12 unchanged lines hidden (view full) ---

512void
513CoprocessorUnusableFault::invoke(ThreadContext *tc)
514{
515#if FULL_SYSTEM
516 DPRINTF(MipsPRA, "%s encountered.\n", name());
517 setExceptionState(tc, 0xb);
518 // The ID of the coprocessor causing the exception is stored in
519 // CoprocessorUnusableFault::coProcID
520 MiscReg cause = tc->readMiscReg(MipsISA::Cause);
521 replaceBits(cause, Cause_CE_HI, Cause_CE_LO, coProcID);
522 tc->setMiscRegNoEffect(MipsISA::Cause, cause);
520 CauseReg cause = tc->readMiscReg(Cause);
521 cause.ce = coProcID;
522 tc->setMiscRegNoEffect(Cause, cause);
523
524 Addr HandlerBase;
525 // Offset 0x180 - General Exception Vector
523
524 Addr HandlerBase;
525 // Offset 0x180 - General Exception Vector
526 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
526 HandlerBase = vect() + tc->readMiscReg(EBase);
527 setHandlerPC(HandlerBase, tc);
528
529#else
530 warn("%s (CP%d) encountered.\n", name(), coProcID);
531#endif
532}
533
534} // namespace MipsISA
535
527 setHandlerPC(HandlerBase, tc);
528
529#else
530 warn("%s (CP%d) encountered.\n", name(), coProcID);
531#endif
532}
533
534} // namespace MipsISA
535