faults.cc (6326:008930a4ace5) faults.cc (6378:4a2ff62c3b4f)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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80FaultName ReservedInstructionFault::_name = "Reserved Instruction Fault";
81FaultVect ReservedInstructionFault::_vect = 0x0180;
82FaultStat ReservedInstructionFault::_count;
83
84FaultName ThreadFault::_name = "Thread Fault";
85FaultVect ThreadFault::_vect = 0x00F1;
86FaultStat ThreadFault::_count;
87
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 71 unchanged lines hidden (view full) ---

80FaultName ReservedInstructionFault::_name = "Reserved Instruction Fault";
81FaultVect ReservedInstructionFault::_vect = 0x0180;
82FaultStat ReservedInstructionFault::_count;
83
84FaultName ThreadFault::_name = "Thread Fault";
85FaultVect ThreadFault::_vect = 0x00F1;
86FaultStat ThreadFault::_count;
87
88
89FaultName ArithmeticFault::_name = "Arithmetic Overflow Exception";
90FaultVect ArithmeticFault::_vect = 0x180;
91FaultStat ArithmeticFault::_count;
92
93FaultName UnimplementedOpcodeFault::_name = "opdec";
94FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
95FaultStat UnimplementedOpcodeFault::_count;
96

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101FaultName TrapFault::_name = "Trap";
102FaultVect TrapFault::_vect = 0x0180;
103FaultStat TrapFault::_count;
104
105FaultName BreakpointFault::_name = "Breakpoint";
106FaultVect BreakpointFault::_vect = 0x0180;
107FaultStat BreakpointFault::_count;
108
88FaultName ArithmeticFault::_name = "Arithmetic Overflow Exception";
89FaultVect ArithmeticFault::_vect = 0x180;
90FaultStat ArithmeticFault::_count;
91
92FaultName UnimplementedOpcodeFault::_name = "opdec";
93FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
94FaultStat UnimplementedOpcodeFault::_count;
95

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100FaultName TrapFault::_name = "Trap";
101FaultVect TrapFault::_vect = 0x0180;
102FaultStat TrapFault::_count;
103
104FaultName BreakpointFault::_name = "Breakpoint";
105FaultVect BreakpointFault::_vect = 0x0180;
106FaultStat BreakpointFault::_count;
107
109
110FaultName ItbInvalidFault::_name = "Invalid TLB Entry Exception (I-Fetch/LW)";
111FaultVect ItbInvalidFault::_vect = 0x0180;
112FaultStat ItbInvalidFault::_count;
113
114FaultName ItbPageFault::_name = "itbmiss";
115FaultVect ItbPageFault::_vect = 0x0181;
116FaultStat ItbPageFault::_count;
117

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163FaultVect IntegerOverflowFault::_vect = 0x0501;
164FaultStat IntegerOverflowFault::_count;
165
166FaultName DspStateDisabledFault::_name = "DSP Disabled Fault";
167FaultVect DspStateDisabledFault::_vect = 0x001a;
168FaultStat DspStateDisabledFault::_count;
169
170#if FULL_SYSTEM
108FaultName ItbInvalidFault::_name = "Invalid TLB Entry Exception (I-Fetch/LW)";
109FaultVect ItbInvalidFault::_vect = 0x0180;
110FaultStat ItbInvalidFault::_count;
111
112FaultName ItbPageFault::_name = "itbmiss";
113FaultVect ItbPageFault::_vect = 0x0181;
114FaultStat ItbPageFault::_count;
115

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161FaultVect IntegerOverflowFault::_vect = 0x0501;
162FaultStat IntegerOverflowFault::_count;
163
164FaultName DspStateDisabledFault::_name = "DSP Disabled Fault";
165FaultVect DspStateDisabledFault::_vect = 0x001a;
166FaultStat DspStateDisabledFault::_count;
167
168#if FULL_SYSTEM
171void MipsFault::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
169void
170MipsFault::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
172{
171{
173 tc->setPC(HandlerBase);
174 tc->setNextPC(HandlerBase+sizeof(MachInst));
175 tc->setNextNPC(HandlerBase+2*sizeof(MachInst));
172 tc->setPC(HandlerBase);
173 tc->setNextPC(HandlerBase + sizeof(MachInst));
174 tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst));
176}
177
175}
176
178void MipsFault::setExceptionState(ThreadContext *tc,uint8_t ExcCode)
177void
178MipsFault::setExceptionState(ThreadContext *tc, uint8_t ExcCode)
179{
179{
180 // modify SRS Ctl - Save CSS, put ESS into CSS
181 MiscReg stat = tc->readMiscReg(MipsISA::Status);
182 if(bits(stat,Status_EXL) != 1 && bits(stat,Status_BEV) != 1)
183 {
184 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
185 MiscReg srs = tc->readMiscReg(MipsISA::SRSCtl);
186 uint8_t CSS,ESS;
187 CSS = bits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO);
188 ESS = bits(srs,SRSCtl_ESS_HI,SRSCtl_ESS_LO);
189 // Move CSS to PSS
190 replaceBits(srs,SRSCtl_PSS_HI,SRSCtl_PSS_LO,CSS);
191 // Move ESS to CSS
192 replaceBits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO,ESS);
193 tc->setMiscRegNoEffect(MipsISA::SRSCtl,srs);
194 //tc->setShadowSet(ESS);
180 // modify SRS Ctl - Save CSS, put ESS into CSS
181 MiscReg stat = tc->readMiscReg(MipsISA::Status);
182 if (bits(stat, Status_EXL) != 1 && bits(stat, Status_BEV) != 1) {
183 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
184 MiscReg srs = tc->readMiscReg(MipsISA::SRSCtl);
185 uint8_t CSS, ESS;
186 CSS = bits(srs, SRSCtl_CSS_HI, SRSCtl_CSS_LO);
187 ESS = bits(srs, SRSCtl_ESS_HI, SRSCtl_ESS_LO);
188 // Move CSS to PSS
189 replaceBits(srs, SRSCtl_PSS_HI, SRSCtl_PSS_LO, CSS);
190 // Move ESS to CSS
191 replaceBits(srs, SRSCtl_CSS_HI, SRSCtl_CSS_LO, ESS);
192 tc->setMiscRegNoEffect(MipsISA::SRSCtl, srs);
195 }
196
193 }
194
197 // set EXL bit (don't care if it is already set!)
198 replaceBits(stat,Status_EXL_HI,Status_EXL_LO,1);
199 tc->setMiscRegNoEffect(MipsISA::Status,stat);
195 // set EXL bit (don't care if it is already set!)
196 replaceBits(stat, Status_EXL_HI, Status_EXL_LO, 1);
197 tc->setMiscRegNoEffect(MipsISA::Status, stat);
200
198
201 // write EPC
202 // warn("Set EPC to %x\n",tc->readPC());
203 // CHECK ME or FIXME or FIX ME or POSSIBLE HACK
204 // Check to see if the exception occurred in the branch delay slot
205 DPRINTF(MipsPRA,"PC: %x, NextPC: %x, NNPC: %x\n",tc->readPC(),tc->readNextPC(),tc->readNextNPC());
206 int C_BD=0;
207 if(tc->readPC() + sizeof(MachInst) != tc->readNextPC()){
208 tc->setMiscRegNoEffect(MipsISA::EPC,tc->readPC()-sizeof(MachInst));
209 // In the branch delay slot? set CAUSE_31
210 C_BD = 1;
211 } else {
212 tc->setMiscRegNoEffect(MipsISA::EPC,tc->readPC());
213 // In the branch delay slot? reset CAUSE_31
214 C_BD = 0;
215 }
199 // write EPC
200 // CHECK ME or FIXME or FIX ME or POSSIBLE HACK
201 // Check to see if the exception occurred in the branch delay slot
202 DPRINTF(MipsPRA, "PC: %x, NextPC: %x, NNPC: %x\n",
203 tc->readPC(), tc->readNextPC(), tc->readNextNPC());
204 int C_BD = 0;
205 if (tc->readPC() + sizeof(MachInst) != tc->readNextPC()) {
206 tc->setMiscRegNoEffect(MipsISA::EPC, tc->readPC() - sizeof(MachInst));
207 // In the branch delay slot? set CAUSE_31
208 C_BD = 1;
209 } else {
210 tc->setMiscRegNoEffect(MipsISA::EPC, tc->readPC());
211 // In the branch delay slot? reset CAUSE_31
212 C_BD = 0;
213 }
216
214
217 // Set Cause_EXCCODE field
218 MiscReg cause = tc->readMiscReg(MipsISA::Cause);
219 replaceBits(cause,Cause_EXCCODE_HI,Cause_EXCCODE_LO,ExcCode);
220 replaceBits(cause,Cause_BD_HI,Cause_BD_LO,C_BD);
221 replaceBits(cause,Cause_CE_HI,Cause_CE_LO,0);
222 tc->setMiscRegNoEffect(MipsISA::Cause,cause);
223
215 // Set Cause_EXCCODE field
216 MiscReg cause = tc->readMiscReg(MipsISA::Cause);
217 replaceBits(cause, Cause_EXCCODE_HI, Cause_EXCCODE_LO, ExcCode);
218 replaceBits(cause, Cause_BD_HI, Cause_BD_LO,C_BD);
219 replaceBits(cause, Cause_CE_HI, Cause_CE_LO,0);
220 tc->setMiscRegNoEffect(MipsISA::Cause, cause);
224}
225
221}
222
226void ArithmeticFault::invoke(ThreadContext *tc)
223void
224ArithmeticFault::invoke(ThreadContext *tc)
227{
225{
228 DPRINTF(MipsPRA,"%s encountered.\n", name());
229 setExceptionState(tc,0xC);
226 DPRINTF(MipsPRA, "%s encountered.\n", name());
227 setExceptionState(tc, 0xC);
230
228
231 // Set new PC
232 Addr HandlerBase;
233 MiscReg stat = tc->readMiscReg(MipsISA::Status);
234 // Here, the handler is dependent on BEV, which is not modified by setExceptionState()
235 if(bits(stat,Status_BEV)==0){ // See MIPS ARM Vol 3, Revision 2, Page 38
236 HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase);
237 }else{
238 HandlerBase = 0xBFC00200;
239 }
240 setHandlerPC(HandlerBase,tc);
241 // warn("Exception Handler At: %x \n",HandlerBase);
229 // Set new PC
230 Addr HandlerBase;
231 MiscReg stat = tc->readMiscReg(MipsISA::Status);
232 // Here, the handler is dependent on BEV, which is not modified by
233 // setExceptionState()
234 if (bits(stat, Status_BEV) == 0 ) {
235 // See MIPS ARM Vol 3, Revision 2, Page 38
236 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
237 } else {
238 HandlerBase = 0xBFC00200;
239 }
240 setHandlerPC(HandlerBase, tc);
242}
243
241}
242
244void StoreAddressErrorFault::invoke(ThreadContext *tc)
243void
244StoreAddressErrorFault::invoke(ThreadContext *tc)
245{
245{
246 DPRINTF(MipsPRA,"%s encountered.\n", name());
247 setExceptionState(tc,0x5);
248 tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
246 DPRINTF(MipsPRA, "%s encountered.\n", name());
247 setExceptionState(tc, 0x5);
248 tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
249
249
250 // Set new PC
251 Addr HandlerBase;
252 HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
253 setHandlerPC(HandlerBase,tc);
254 // warn("Exception Handler At: %x \n",HandlerBase);
255 // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
256
250 // Set new PC
251 Addr HandlerBase;
252 // Offset 0x180 - General Exception Vector
253 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
254 setHandlerPC(HandlerBase, tc);
257}
258
255}
256
259void TrapFault::invoke(ThreadContext *tc)
257void
258TrapFault::invoke(ThreadContext *tc)
260{
259{
261 DPRINTF(MipsPRA,"%s encountered.\n", name());
262 // warn("%s encountered.\n", name());
263 setExceptionState(tc,0xD);
260 DPRINTF(MipsPRA, "%s encountered.\n", name());
261 setExceptionState(tc, 0xD);
264
262
265 // Set new PC
266 Addr HandlerBase;
267 HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
268 setHandlerPC(HandlerBase,tc);
269 // warn("Exception Handler At: %x \n",HandlerBase);
270 // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
263 // Set new PC
264 Addr HandlerBase;
265 // Offset 0x180 - General Exception Vector
266 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
267 setHandlerPC(HandlerBase, tc);
271}
272
268}
269
273void BreakpointFault::invoke(ThreadContext *tc)
270void
271BreakpointFault::invoke(ThreadContext *tc)
274{
272{
275 setExceptionState(tc,0x9);
273 setExceptionState(tc, 0x9);
276
274
277 // Set new PC
278 Addr HandlerBase;
279 HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
280 setHandlerPC(HandlerBase,tc);
281 // warn("Exception Handler At: %x \n",HandlerBase);
282 // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
283
275 // Set new PC
276 Addr HandlerBase;
277 // Offset 0x180 - General Exception Vector
278 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
279 setHandlerPC(HandlerBase, tc);
284}
285
280}
281
286void DtbInvalidFault::invoke(ThreadContext *tc)
282void
283DtbInvalidFault::invoke(ThreadContext *tc)
287{
284{
288 DPRINTF(MipsPRA,"%s encountered.\n", name());
289 // warn("%s encountered.\n", name());
290 tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
291 MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
292 replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
293 replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
294 replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
295 tc->setMiscRegNoEffect(MipsISA::EntryHi,eh);
296 MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
297 replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
298 tc->setMiscRegNoEffect(MipsISA::Context,ctxt);
299 setExceptionState(tc,0x3);
285 DPRINTF(MipsPRA, "%s encountered.\n", name());
300
286
287 tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
288 MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
289 replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
290 replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
291 replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
292 tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
293 MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
294 replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
295 tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
296 setExceptionState(tc, 0x3);
301
297
302 // Set new PC
303 Addr HandlerBase;
304 HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
305 setHandlerPC(HandlerBase,tc);
306 // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
298
299 // Set new PC
300 Addr HandlerBase;
301 // Offset 0x180 - General Exception Vector
302 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
303 setHandlerPC(HandlerBase,tc);
307}
308
304}
305
309void AddressErrorFault::invoke(ThreadContext *tc)
306void
307AddressErrorFault::invoke(ThreadContext *tc)
310{
308{
311 DPRINTF(MipsPRA,"%s encountered.\n", name());
312 setExceptionState(tc,0x4);
313 tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
309 DPRINTF(MipsPRA, "%s encountered.\n", name());
310 setExceptionState(tc, 0x4);
311 tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
314
312
315 // Set new PC
316 Addr HandlerBase;
317 HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
318 setHandlerPC(HandlerBase,tc);
313 // Set new PC
314 Addr HandlerBase;
315 // Offset 0x180 - General Exception Vector
316 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
317 setHandlerPC(HandlerBase, tc);
319}
320
318}
319
321void ItbInvalidFault::invoke(ThreadContext *tc)
320void
321ItbInvalidFault::invoke(ThreadContext *tc)
322{
322{
323 DPRINTF(MipsPRA,"%s encountered.\n", name());
324 setExceptionState(tc,0x2);
325 tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
326 MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
327 replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
328 replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
329 replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
330 tc->setMiscRegNoEffect(MipsISA::EntryHi,eh);
331 MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
332 replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
333 tc->setMiscRegNoEffect(MipsISA::Context,ctxt);
323 DPRINTF(MipsPRA, "%s encountered.\n", name());
324 setExceptionState(tc, 0x2);
325 tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
326 MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
327 replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
328 replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
329 replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
330 tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
331 MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
332 replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
333 tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
334
335
334
335
336 // Set new PC
337 Addr HandlerBase;
338 HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
339 setHandlerPC(HandlerBase,tc);
340 DPRINTF(MipsPRA,"Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
336 // Set new PC
337 Addr HandlerBase;
338 // Offset 0x180 - General Exception Vector
339 HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase);
340 setHandlerPC(HandlerBase,tc);
341 DPRINTF(MipsPRA,"Exception Handler At: %x , EPC set to %x\n",
342 HandlerBase, tc->readMiscReg(MipsISA::EPC));
341}
342
343}
344
343void ItbRefillFault::invoke(ThreadContext *tc)
345void
346ItbRefillFault::invoke(ThreadContext *tc)
344{
347{
345 DPRINTF(MipsPRA,"%s encountered (%x).\n", name(),BadVAddr);
346 Addr HandlerBase;
347 tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
348 MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
349 replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
350 replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
351 replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
352 tc->setMiscRegNoEffect(MipsISA::EntryHi,eh);
353 MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
354 replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
355 tc->setMiscRegNoEffect(MipsISA::Context,ctxt);
348 DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), BadVAddr);
349 Addr HandlerBase;
350 tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
351 MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
352 replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
353 replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
354 replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
355 tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
356 MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
357 replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
358 tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
356
359
357 MiscReg stat = tc->readMiscReg(MipsISA::Status);
358 // Since handler depends on EXL bit, must check EXL bit before setting it!!
359 if(bits(stat,Status_EXL)==1){ // See MIPS ARM Vol 3, Revision 2, Page 38
360 HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
361 }else{
362 HandlerBase = tc->readMiscReg(MipsISA::EBase); // Offset 0x000
363 }
360 MiscReg stat = tc->readMiscReg(MipsISA::Status);
361 // Since handler depends on EXL bit, must check EXL bit before setting it!!
362 // See MIPS ARM Vol 3, Revision 2, Page 38
363 if (bits(stat, Status_EXL) == 1) {
364 // Offset 0x180 - General Exception Vector
365 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
366 } else {
367 // Offset 0x000
368 HandlerBase = tc->readMiscReg(MipsISA::EBase);
369 }
364
370
365 setExceptionState(tc,0x2);
366 setHandlerPC(HandlerBase,tc);
371 setExceptionState(tc, 0x2);
372 setHandlerPC(HandlerBase, tc);
367}
368
373}
374
369void DtbRefillFault::invoke(ThreadContext *tc)
375void
376DtbRefillFault::invoke(ThreadContext *tc)
370{
377{
371 // Set new PC
372 DPRINTF(MipsPRA,"%s encountered.\n", name());
373 Addr HandlerBase;
374 tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
375 MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
376 replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
377 replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
378 replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
379 tc->setMiscRegNoEffect(MipsISA::EntryHi,eh);
380 MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
381 replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
382 tc->setMiscRegNoEffect(MipsISA::Context,ctxt);
378 // Set new PC
379 DPRINTF(MipsPRA, "%s encountered.\n", name());
380 Addr HandlerBase;
381 tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
382 MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
383 replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
384 replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
385 replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
386 tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
387 MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
388 replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
389 tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
383
390
384 MiscReg stat = tc->readMiscReg(MipsISA::Status);
385 // Since handler depends on EXL bit, must check EXL bit before setting it!!
386 if(bits(stat,Status_EXL)==1){ // See MIPS ARM Vol 3, Revision 2, Page 38
387 HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
388 }else{
389 HandlerBase = tc->readMiscReg(MipsISA::EBase); // Offset 0x000
390 }
391 MiscReg stat = tc->readMiscReg(MipsISA::Status);
392 // Since handler depends on EXL bit, must check EXL bit before setting it!!
393 // See MIPS ARM Vol 3, Revision 2, Page 38
394 if(bits(stat, Status_EXL) == 1) {
395 // Offset 0x180 - General Exception Vector
396 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
397 } else {
398 // Offset 0x000
399 HandlerBase = tc->readMiscReg(MipsISA::EBase);
400 }
391
401
402 setExceptionState(tc, 0x3);
392
403
393 setExceptionState(tc,0x3);
394
395 setHandlerPC(HandlerBase,tc);
404 setHandlerPC(HandlerBase, tc);
396}
397
405}
406
398void TLBModifiedFault::invoke(ThreadContext *tc)
407void
408TLBModifiedFault::invoke(ThreadContext *tc)
399{
409{
400 DPRINTF(MipsPRA,"%s encountered.\n", name());
401 tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
402 MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
403 replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
404 replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
405 replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
406 tc->setMiscRegNoEffect(MipsISA::EntryHi,eh);
407 MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
408 replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
409 tc->setMiscRegNoEffect(MipsISA::Context,ctxt);
410 DPRINTF(MipsPRA, "%s encountered.\n", name());
411 tc->setMiscRegNoEffect(MipsISA::BadVAddr, BadVAddr);
412 MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
413 replaceBits(eh, EntryHi_ASID_HI, EntryHi_ASID_LO, EntryHi_Asid);
414 replaceBits(eh, EntryHi_VPN2_HI, EntryHi_VPN2_LO, EntryHi_VPN2);
415 replaceBits(eh, EntryHi_VPN2X_HI, EntryHi_VPN2X_LO, EntryHi_VPN2X);
416 tc->setMiscRegNoEffect(MipsISA::EntryHi, eh);
417 MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
418 replaceBits(ctxt, Context_BadVPN2_HI, Context_BadVPN2_LO, Context_BadVPN2);
419 tc->setMiscRegNoEffect(MipsISA::Context, ctxt);
410
411 // Set new PC
420
421 // Set new PC
412 Addr HandlerBase;
413 HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
414 setExceptionState(tc,0x1);
415 setHandlerPC(HandlerBase,tc);
416 // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
422 Addr HandlerBase;
423 // Offset 0x180 - General Exception Vector
424 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
425 setExceptionState(tc, 0x1);
426 setHandlerPC(HandlerBase, tc);
417
418}
419
427
428}
429
420void SystemCallFault::invoke(ThreadContext *tc)
430void
431SystemCallFault::invoke(ThreadContext *tc)
421{
432{
422 DPRINTF(MipsPRA,"%s encountered.\n", name());
423 setExceptionState(tc,0x8);
433 DPRINTF(MipsPRA, "%s encountered.\n", name());
434 setExceptionState(tc, 0x8);
424
435
425 // Set new PC
426 Addr HandlerBase;
427 HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
428 setHandlerPC(HandlerBase,tc);
429 // warn("Exception Handler At: %x \n",HandlerBase);
430 // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
431
436 // Set new PC
437 Addr HandlerBase;
438 // Offset 0x180 - General Exception Vector
439 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
440 setHandlerPC(HandlerBase, tc);
432}
433
441}
442
434void InterruptFault::invoke(ThreadContext *tc)
443void
444InterruptFault::invoke(ThreadContext *tc)
435{
436#if FULL_SYSTEM
445{
446#if FULL_SYSTEM
437 DPRINTF(MipsPRA,"%s encountered.\n", name());
438 setExceptionState(tc,0x0A);
439 Addr HandlerBase;
447 DPRINTF(MipsPRA, "%s encountered.\n", name());
448 setExceptionState(tc, 0x0A);
449 Addr HandlerBase;
440
450
451 uint8_t IV = bits(tc->readMiscRegNoEffect(MipsISA::Cause), Cause_IV);
452 if (IV) {
453 // Offset 200 for release 2
454 HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
455 } else {
456 //Ofset at 180 for release 1
457 HandlerBase = vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
458 }
441
459
442 uint8_t IV = bits(tc->readMiscRegNoEffect(MipsISA::Cause),Cause_IV);
443 if (IV)// Offset 200 for release 2
444 HandlerBase= 0x20 + vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
445 else//Ofset at 180 for release 1
446 HandlerBase= vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
447
448 setHandlerPC(HandlerBase,tc);
460 setHandlerPC(HandlerBase, tc);
449#endif
450}
451
452#endif // FULL_SYSTEM
453
461#endif
462}
463
464#endif // FULL_SYSTEM
465
454void ResetFault::invoke(ThreadContext *tc)
466void
467ResetFault::invoke(ThreadContext *tc)
455{
456#if FULL_SYSTEM
468{
469#if FULL_SYSTEM
457 DPRINTF(MipsPRA,"%s encountered.\n", name());
458 /* All reset activity must be invoked from here */
459 tc->setPC(vect());
460 tc->setNextPC(vect()+sizeof(MachInst));
461 tc->setNextNPC(vect()+sizeof(MachInst)+sizeof(MachInst));
462 DPRINTF(MipsPRA,"(%x) - ResetFault::invoke : PC set to %x",(unsigned)tc,(unsigned)tc->readPC());
470 DPRINTF(MipsPRA, "%s encountered.\n", name());
471 /* All reset activity must be invoked from here */
472 tc->setPC(vect());
473 tc->setNextPC(vect() + sizeof(MachInst));
474 tc->setNextNPC(vect() + sizeof(MachInst) + sizeof(MachInst));
475 DPRINTF(MipsPRA, "(%x) - ResetFault::invoke : PC set to %x",
476 (unsigned)tc, (unsigned)tc->readPC());
463#endif
464
477#endif
478
465 // Set Coprocessor 1 (Floating Point) To Usable
466 tc->setMiscReg(MipsISA::Status, MipsISA::Status | 0x20000000);
479 // Set Coprocessor 1 (Floating Point) To Usable
480 tc->setMiscReg(MipsISA::Status, MipsISA::Status | 0x20000000);
467}
468
481}
482
469void ReservedInstructionFault::invoke(ThreadContext *tc)
483void
484ReservedInstructionFault::invoke(ThreadContext *tc)
470{
471#if FULL_SYSTEM
485{
486#if FULL_SYSTEM
472 DPRINTF(MipsPRA,"%s encountered.\n", name());
473 setExceptionState(tc,0x0A);
474 Addr HandlerBase;
475 HandlerBase= vect() + tc->readMiscRegNoEffect(MipsISA::EBase); // Offset 0x180 - General Exception Vector
476 setHandlerPC(HandlerBase,tc);
487 DPRINTF(MipsPRA, "%s encountered.\n", name());
488 setExceptionState(tc, 0x0A);
489 Addr HandlerBase;
490 // Offset 0x180 - General Exception Vector
491 HandlerBase = vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
492 setHandlerPC(HandlerBase, tc);
477#else
478 panic("%s encountered.\n", name());
479#endif
480}
481
493#else
494 panic("%s encountered.\n", name());
495#endif
496}
497
482void ThreadFault::invoke(ThreadContext *tc)
498void
499ThreadFault::invoke(ThreadContext *tc)
483{
500{
484 DPRINTF(MipsPRA,"%s encountered.\n", name());
485 panic("%s encountered.\n", name());
501 DPRINTF(MipsPRA, "%s encountered.\n", name());
502 panic("%s encountered.\n", name());
486}
487
503}
504
488void DspStateDisabledFault::invoke(ThreadContext *tc)
505void
506DspStateDisabledFault::invoke(ThreadContext *tc)
489{
507{
490 DPRINTF(MipsPRA,"%s encountered.\n", name());
491 panic("%s encountered.\n", name());
508 DPRINTF(MipsPRA, "%s encountered.\n", name());
509 panic("%s encountered.\n", name());
492}
493
510}
511
494void CoprocessorUnusableFault::invoke(ThreadContext *tc)
512void
513CoprocessorUnusableFault::invoke(ThreadContext *tc)
495{
496#if FULL_SYSTEM
514{
515#if FULL_SYSTEM
497 DPRINTF(MipsPRA,"%s encountered.\n", name());
498 setExceptionState(tc,0xb);
499 /* The ID of the coprocessor causing the exception is stored in CoprocessorUnusableFault::coProcID */
500 MiscReg cause = tc->readMiscReg(MipsISA::Cause);
501 replaceBits(cause,Cause_CE_HI,Cause_CE_LO,coProcID);
502 tc->setMiscRegNoEffect(MipsISA::Cause,cause);
516 DPRINTF(MipsPRA, "%s encountered.\n", name());
517 setExceptionState(tc, 0xb);
518 // The ID of the coprocessor causing the exception is stored in
519 // CoprocessorUnusableFault::coProcID
520 MiscReg cause = tc->readMiscReg(MipsISA::Cause);
521 replaceBits(cause, Cause_CE_HI, Cause_CE_LO, coProcID);
522 tc->setMiscRegNoEffect(MipsISA::Cause, cause);
503
523
504 Addr HandlerBase;
505 HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
506 setHandlerPC(HandlerBase,tc);
524 Addr HandlerBase;
525 // Offset 0x180 - General Exception Vector
526 HandlerBase = vect() + tc->readMiscReg(MipsISA::EBase);
527 setHandlerPC(HandlerBase, tc);
507
528
508 // warn("Status: %x, Cause: %x\n",tc->readMiscReg(MipsISA::Status),tc->readMiscReg(MipsISA::Cause));
509#else
510 warn("%s (CP%d) encountered.\n", name(), coProcID);
511#endif
512}
513
514} // namespace MipsISA
515
529#else
530 warn("%s (CP%d) encountered.\n", name(), coProcID);
531#endif
532}
533
534} // namespace MipsISA
535