faults.cc (5268:5bfc53fe60e7) faults.cc (6326:008930a4ace5)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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430 // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
431
432}
433
434void InterruptFault::invoke(ThreadContext *tc)
435{
436#if FULL_SYSTEM
437 DPRINTF(MipsPRA,"%s encountered.\n", name());
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 421 unchanged lines hidden (view full) ---

430 // warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
431
432}
433
434void InterruptFault::invoke(ThreadContext *tc)
435{
436#if FULL_SYSTEM
437 DPRINTF(MipsPRA,"%s encountered.\n", name());
438 //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil
439 setExceptionState(tc,0x0A);
440 Addr HandlerBase;
441
442
443 uint8_t IV = bits(tc->readMiscRegNoEffect(MipsISA::Cause),Cause_IV);
444 if (IV)// Offset 200 for release 2
445 HandlerBase= 0x20 + vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
446 else//Ofset at 180 for release 1

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466 // Set Coprocessor 1 (Floating Point) To Usable
467 tc->setMiscReg(MipsISA::Status, MipsISA::Status | 0x20000000);
468}
469
470void ReservedInstructionFault::invoke(ThreadContext *tc)
471{
472#if FULL_SYSTEM
473 DPRINTF(MipsPRA,"%s encountered.\n", name());
438 setExceptionState(tc,0x0A);
439 Addr HandlerBase;
440
441
442 uint8_t IV = bits(tc->readMiscRegNoEffect(MipsISA::Cause),Cause_IV);
443 if (IV)// Offset 200 for release 2
444 HandlerBase= 0x20 + vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
445 else//Ofset at 180 for release 1

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465 // Set Coprocessor 1 (Floating Point) To Usable
466 tc->setMiscReg(MipsISA::Status, MipsISA::Status | 0x20000000);
467}
468
469void ReservedInstructionFault::invoke(ThreadContext *tc)
470{
471#if FULL_SYSTEM
472 DPRINTF(MipsPRA,"%s encountered.\n", name());
474 //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil
475 setExceptionState(tc,0x0A);
476 Addr HandlerBase;
477 HandlerBase= vect() + tc->readMiscRegNoEffect(MipsISA::EBase); // Offset 0x180 - General Exception Vector
478 setHandlerPC(HandlerBase,tc);
479#else
480 panic("%s encountered.\n", name());
481#endif
482}

--- 35 unchanged lines hidden --- 		473 setExceptionState(tc,0x0A);
474 Addr HandlerBase;
475 HandlerBase= vect() + tc->readMiscRegNoEffect(MipsISA::EBase); // Offset 0x180 - General Exception Vector
476 setHandlerPC(HandlerBase,tc);
477#else
478 panic("%s encountered.\n", name());
479#endif
480}

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