faults.cc (2665:a124942bacb8) | faults.cc (2680:246e7104f744) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 15 unchanged lines hidden (view full) --- 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Korey Sewell 29 */ 30 31#include "arch/mips/faults.hh" | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 15 unchanged lines hidden (view full) --- 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Korey Sewell 29 */ 30 31#include "arch/mips/faults.hh" |
32#include "cpu/exec_context.hh" | 32#include "cpu/thread_context.hh" |
33#include "cpu/base.hh" 34#include "base/trace.hh" 35 36namespace MipsISA 37{ 38 39FaultName MachineCheckFault::_name = "Machine Check"; 40FaultVect MachineCheckFault::_vect = 0x0401; --- 56 unchanged lines hidden (view full) --- 97FaultStat PalFault::_count; 98 99FaultName IntegerOverflowFault::_name = "intover"; 100FaultVect IntegerOverflowFault::_vect = 0x0501; 101FaultStat IntegerOverflowFault::_count; 102 103#if FULL_SYSTEM 104 | 33#include "cpu/base.hh" 34#include "base/trace.hh" 35 36namespace MipsISA 37{ 38 39FaultName MachineCheckFault::_name = "Machine Check"; 40FaultVect MachineCheckFault::_vect = 0x0401; --- 56 unchanged lines hidden (view full) --- 97FaultStat PalFault::_count; 98 99FaultName IntegerOverflowFault::_name = "intover"; 100FaultVect IntegerOverflowFault::_vect = 0x0501; 101FaultStat IntegerOverflowFault::_count; 102 103#if FULL_SYSTEM 104 |
105void MipsFault::invoke(ExecContext * xc) | 105void MipsFault::invoke(ThreadContext * tc) |
106{ | 106{ |
107 FaultBase::invoke(xc); | 107 FaultBase::invoke(tc); |
108 countStat()++; 109 110 // exception restart address | 108 countStat()++; 109 110 // exception restart address |
111 if (setRestartAddress() || !xc->inPalMode()) 112 xc->setMiscReg(MipsISA::IPR_EXC_ADDR, xc->readPC()); | 111 if (setRestartAddress() || !tc->inPalMode()) 112 tc->setMiscReg(MipsISA::IPR_EXC_ADDR, tc->readPC()); |
113 114 if (skipFaultingInstruction()) { 115 // traps... skip faulting instruction. | 113 114 if (skipFaultingInstruction()) { 115 // traps... skip faulting instruction. |
116 xc->setMiscReg(MipsISA::IPR_EXC_ADDR, 117 xc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4); | 116 tc->setMiscReg(MipsISA::IPR_EXC_ADDR, 117 tc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4); |
118 } 119 | 118 } 119 |
120 xc->setPC(xc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect()); 121 xc->setNextPC(xc->readPC() + sizeof(MachInst)); | 120 tc->setPC(tc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect()); 121 tc->setNextPC(tc->readPC() + sizeof(MachInst)); |
122} 123 | 122} 123 |
124void ArithmeticFault::invoke(ExecContext * xc) | 124void ArithmeticFault::invoke(ThreadContext * tc) |
125{ | 125{ |
126 FaultBase::invoke(xc); | 126 FaultBase::invoke(tc); |
127 panic("Arithmetic traps are unimplemented!"); 128} 129 130#endif 131 132} // namespace MipsISA 133 | 127 panic("Arithmetic traps are unimplemented!"); 128} 129 130#endif 131 132} // namespace MipsISA 133 |