1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 34 unchanged lines hidden (view full) --- 43#include "sim/process.hh" 44#endif 45 46namespace MipsISA 47{ 48 49typedef MipsFaultBase::FaultVals FaultVals; 50 |
51template <> FaultVals MipsFault<SystemCallFault>::vals = |
52 { "Syscall", 0x180, ExcCodeSys }; |
53 |
54template <> FaultVals MipsFault<ReservedInstructionFault>::vals = |
55 { "Reserved Instruction Fault", 0x180, ExcCodeRI }; |
56 57template <> FaultVals MipsFault<ThreadFault>::vals = |
58 { "Thread Fault", 0x180, ExcCodeDummy }; |
59 60template <> FaultVals MipsFault<IntegerOverflowFault>::vals = |
61 { "Integer Overflow Exception", 0x180, ExcCodeOv }; |
62 |
63template <> FaultVals MipsFault<TrapFault>::vals = |
64 { "Trap", 0x180, ExcCodeTr }; |
65 66template <> FaultVals MipsFault<BreakpointFault>::vals = |
67 { "Breakpoint", 0x180, ExcCodeBp }; |
68 |
69template <> FaultVals MipsFault<DspStateDisabledFault>::vals = 70 { "DSP Disabled Fault", 0x180, ExcCodeDummy }; 71 72template <> FaultVals MipsFault<MachineCheckFault>::vals = 73 { "Machine Check", 0x180, ExcCodeMCheck }; 74 75template <> FaultVals MipsFault<ResetFault>::vals = 76 { "Reset Fault", 0x000, ExcCodeDummy }; 77 78template <> FaultVals MipsFault<SoftResetFault>::vals = 79 { "Soft Reset Fault", 0x000, ExcCodeDummy }; 80 81template <> FaultVals MipsFault<NonMaskableInterrupt>::vals = 82 { "Non Maskable Interrupt", 0x000, ExcCodeDummy }; 83 84template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals = 85 { "Coprocessor Unusable Fault", 0x180, ExcCodeCpU }; 86 87template <> FaultVals MipsFault<InterruptFault>::vals = 88 { "Interrupt", 0x000, ExcCodeInt }; 89 90template <> FaultVals MipsFault<AddressErrorFault>::vals = 91 { "Address Error", 0x180, ExcCodeDummy }; 92 |
93template <> FaultVals MipsFault<TlbInvalidFault>::vals = |
94 { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy }; |
95 96template <> FaultVals MipsFault<TlbRefillFault>::vals = |
97 { "TLB Refill Exception", 0x180, ExcCodeDummy }; |
98 99template <> FaultVals MipsFault<TlbModifiedFault>::vals = |
100 { "TLB Modified Exception", 0x180, ExcCodeMod }; |
101 |
102void 103MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode) 104{ 105 // modify SRS Ctl - Save CSS, put ESS into CSS 106 StatusReg status = tc->readMiscReg(MISCREG_STATUS); 107 if (status.exl != 1 && status.bev != 1) { 108 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set 109 SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL); --- 16 unchanged lines hidden (view full) --- 126 // Set Cause_EXCCODE field 127 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 128 cause.excCode = excCode; 129 cause.bd = delay_slot ? 1 : 0; 130 cause.ce = 0; 131 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 132} 133 |
134void |
135MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst) |
136{ |
137 if (FULL_SYSTEM) { 138 DPRINTF(MipsPRA, "Fault %s encountered.\n", name()); 139 setExceptionState(tc, code()); 140 tc->pcState(vect(tc)); |
141 } else { |
142 panic("Fault %s encountered.\n", name()); |
143 } 144} 145 146void |
147ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst) |
148{ |
149 if (FULL_SYSTEM) { 150 DPRINTF(MipsPRA, "%s encountered.\n", name()); 151 /* All reset activity must be invoked from here */ 152 Addr handler = vect(tc); 153 tc->pcState(handler); 154 DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler); |
155 } |
156 |
157 // Set Coprocessor 1 (Floating Point) To Usable 158 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); 159 status.cu.cu1 = 1; 160 tc->setMiscReg(MISCREG_STATUS, status); 161} 162 163void |
164SoftResetFault::invoke(ThreadContext *tc, StaticInstPtr inst) |
165{ |
166 panic("Soft reset not implemented.\n"); |
167} 168 169void |
170NonMaskableInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst) |
171{ |
172 panic("Non maskable interrupt not implemented.\n"); |
173} 174 |
175} // namespace MipsISA 176 |