1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 77 unchanged lines hidden (view full) --- 86 { "Breakpoint", 0x0180 }; 87 88template <> FaultVals MipsFault<TlbInvalidFault>::vals = 89 { "Invalid TLB Entry Exception", 0x0180 }; 90 91template <> FaultVals MipsFault<TlbRefillFault>::vals = 92 { "TLB Refill Exception", 0x0180 }; 93 |
94template <> FaultVals MipsFault<TlbModifiedFault>::vals = |
95 { "TLB Modified Exception", 0x0180 }; 96 97template <> FaultVals MipsFault<DspStateDisabledFault>::vals = 98 { "DSP Disabled Fault", 0x001a }; 99 100void 101MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode) 102{ --- 76 unchanged lines hidden (view full) --- 179 // Set new PC 180 Addr HandlerBase; 181 // Offset 0x180 - General Exception Vector 182 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 183 setHandlerPC(HandlerBase, tc); 184} 185 186void |
187AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst) |
188{ 189 DPRINTF(MipsPRA, "%s encountered.\n", name()); |
190 setExceptionState(tc, store ? 0x5 : 0x4); 191 tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr); |
192 |
193 // Set new PC 194 Addr HandlerBase; 195 // Offset 0x180 - General Exception Vector 196 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 197 setHandlerPC(HandlerBase, tc); 198} 199 200void |
201TlbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst) |
202{ |
203 setTlbExceptionState(tc, store ? 0x3 : 0x2); |
204 // Set new PC 205 Addr HandlerBase; 206 // Offset 0x180 - General Exception Vector 207 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 208 setHandlerPC(HandlerBase, tc); 209} 210 211void 212TlbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst) 213{ |
214 // Since handler depends on EXL bit, must check EXL bit before setting it!! 215 StatusReg status = tc->readMiscReg(MISCREG_STATUS); |
216 |
217 setTlbExceptionState(tc, store ? 0x3 : 0x2); |
218 |
219 // See MIPS ARM Vol 3, Revision 2, Page 38 220 if (status.exl == 1) { 221 // Offset 0x180 - General Exception Vector 222 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); 223 } else { 224 // Offset 0x000 225 HandlerBase = tc->readMiscReg(MISCREG_EBASE); 226 } 227 setHandlerPC(HandlerBase, tc); 228} 229 230void |
231TlbModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst) |
232{ |
233 setTlbExceptionState(tc, 0x1); |
234 |
235 // Set new PC 236 Addr HandlerBase; 237 // Offset 0x180 - General Exception Vector 238 HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); |
239 setHandlerPC(HandlerBase, tc); |
240} 241 242void 243SystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst) 244{ 245 DPRINTF(MipsPRA, "%s encountered.\n", name()); 246 setExceptionState(tc, 0x8); 247 --- 101 unchanged lines hidden --- |