1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 83 unchanged lines hidden (view full) --- 92 { "TLB Refill Exception", 0x0180 }; 93 94template <> FaultVals MipsFault<TLBModifiedFault>::vals = 95 { "TLB Modified Exception", 0x0180 }; 96 97template <> FaultVals MipsFault<DspStateDisabledFault>::vals = 98 { "DSP Disabled Fault", 0x001a }; 99 |
100void |
101MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode) 102{ 103 // modify SRS Ctl - Save CSS, put ESS into CSS 104 StatusReg status = tc->readMiscReg(MISCREG_STATUS); 105 if (status.exl != 1 && status.bev != 1) { 106 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set 107 SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL); 108 srsCtl.pss = srsCtl.css; 109 srsCtl.css = srsCtl.ess; 110 tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl); 111 } 112 113 // set EXL bit (don't care if it is already set!) 114 status.exl = 1; 115 tc->setMiscRegNoEffect(MISCREG_STATUS, status); 116 117 // write EPC |
118 PCState pc = tc->pcState(); 119 DPRINTF(MipsPRA, "PC: %s\n", pc); 120 bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc(); 121 tc->setMiscRegNoEffect(MISCREG_EPC, 122 pc.pc() - delay_slot ? sizeof(MachInst) : 0); |
123 124 // Set Cause_EXCCODE field 125 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 126 cause.excCode = excCode; |
127 cause.bd = delay_slot ? 1 : 0; |
128 cause.ce = 0; 129 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); 130} 131 |
132#if FULL_SYSTEM |
133void |
134MipsFaultBase::setHandlerPC(Addr HandlerBase, ThreadContext *tc) 135{ 136 tc->setPC(HandlerBase); 137 tc->setNextPC(HandlerBase + sizeof(MachInst)); 138 tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst)); 139} 140 141void |
142IntegerOverflowFault::invoke(ThreadContext *tc, StaticInstPtr inst) 143{ 144 DPRINTF(MipsPRA, "%s encountered.\n", name()); 145 setExceptionState(tc, 0xC); 146 147 // Set new PC 148 Addr HandlerBase; 149 StatusReg status = tc->readMiscReg(MISCREG_STATUS); --- 235 unchanged lines hidden --- |