1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 32 unchanged lines hidden (view full) --- 41#if !FULL_SYSTEM 42#include "mem/page_table.hh" 43#include "sim/process.hh" 44#endif 45 46namespace MipsISA 47{ 48 |
49typedef MipsFaultBase::FaultVals FaultVals; |
50 |
51template <> FaultVals MipsFault<MachineCheckFault>::vals = 52 { "Machine Check", 0x0401 }; |
53 |
54template <> FaultVals MipsFault<AlignmentFault>::vals = 55 { "Alignment", 0x0301 }; 56 57template <> FaultVals MipsFault<ResetFault>::vals = |
58#if FULL_SYSTEM |
59 { "Reset Fault", 0xBFC00000}; |
60#else |
61 { "Reset Fault", 0x001}; |
62#endif |
63 |
64template <> FaultVals MipsFault<AddressErrorFault>::vals = 65 { "Address Error", 0x0180 }; |
66 |
67template <> FaultVals MipsFault<StoreAddressErrorFault>::vals = 68 { "Store Address Error", 0x0180 }; |
69 |
70template <> FaultVals MipsFault<SystemCallFault>::vals = 71 { "Syscall", 0x0180 }; |
72 |
73template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals = 74 { "Coprocessor Unusable Fault", 0x180 }; |
75 |
76template <> FaultVals MipsFault<ReservedInstructionFault>::vals = 77 { "Reserved Instruction Fault", 0x0180 }; |
78 |
79template <> FaultVals MipsFault<ThreadFault>::vals = 80 { "Thread Fault", 0x00F1 }; |
81 |
82template <> FaultVals MipsFault<ArithmeticFault>::vals = 83 { "Arithmetic Overflow Exception", 0x180 }; |
84 |
85template <> FaultVals MipsFault<UnimplementedOpcodeFault>::vals = 86 { "opdec", 0x0481 }; |
87 |
88template <> FaultVals MipsFault<InterruptFault>::vals = 89 { "interrupt", 0x0180 }; |
90 |
91template <> FaultVals MipsFault<TrapFault>::vals = 92 { "Trap", 0x0180 }; |
93 |
94template <> FaultVals MipsFault<BreakpointFault>::vals = 95 { "Breakpoint", 0x0180 }; |
96 |
97template <> FaultVals MipsFault<ItbInvalidFault>::vals = 98 { "Invalid TLB Entry Exception (I-Fetch/LW)", 0x0180 }; |
99 |
100template <> FaultVals MipsFault<ItbPageFault>::vals = 101 { "itbmiss", 0x0181 }; |
102 |
103template <> FaultVals MipsFault<ItbMissFault>::vals = 104 { "itbmiss", 0x0181 }; |
105 |
106template <> FaultVals MipsFault<ItbAcvFault>::vals = 107 { "iaccvio", 0x0081 }; |
108 |
109template <> FaultVals MipsFault<ItbRefillFault>::vals = 110 { "TLB Refill Exception (I-Fetch/LW)", 0x0180 }; |
111 |
112template <> FaultVals MipsFault<NDtbMissFault>::vals = 113 { "dtb_miss_single", 0x0201 }; |
114 |
115template <> FaultVals MipsFault<PDtbMissFault>::vals = 116 { "dtb_miss_double", 0x0281 }; |
117 |
118template <> FaultVals MipsFault<DtbPageFault>::vals = 119 { "dfault", 0x0381 }; |
120 |
121template <> FaultVals MipsFault<DtbAcvFault>::vals = 122 { "dfault", 0x0381 }; |
123 |
124template <> FaultVals MipsFault<DtbInvalidFault>::vals = 125 { "Invalid TLB Entry Exception (Store)", 0x0180 }; |
126 |
127template <> FaultVals MipsFault<DtbRefillFault>::vals = 128 { "TLB Refill Exception (Store)", 0x0180 }; |
129 |
130template <> FaultVals MipsFault<TLBModifiedFault>::vals = 131 { "TLB Modified Exception", 0x0180 }; |
132 |
133template <> FaultVals MipsFault<FloatEnableFault>::vals = 134 { "float_enable_fault", 0x0581 }; |
135 |
136template <> FaultVals MipsFault<IntegerOverflowFault>::vals = 137 { "Integer Overflow Fault", 0x0501 }; |
138 |
139template <> FaultVals MipsFault<DspStateDisabledFault>::vals = 140 { "DSP Disabled Fault", 0x001a }; |
141 |
142#if FULL_SYSTEM 143void |
144MipsFaultBase::setHandlerPC(Addr HandlerBase, ThreadContext *tc) |
145{ 146 tc->setPC(HandlerBase); 147 tc->setNextPC(HandlerBase + sizeof(MachInst)); 148 tc->setNextNPC(HandlerBase + 2 * sizeof(MachInst)); 149} 150 151void |
152MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode) |
153{ 154 // modify SRS Ctl - Save CSS, put ESS into CSS 155 StatusReg status = tc->readMiscReg(MISCREG_STATUS); 156 if (status.exl != 1 && status.bev != 1) { 157 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set 158 SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL); 159 srsCtl.pss = srsCtl.css; 160 srsCtl.css = srsCtl.ess; --- 349 unchanged lines hidden --- |