1/* 2 * Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved 3 * 4 * This software is part of the M5 simulator. 5 * 6 * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 7 * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 8 * TO THESE TERMS AND CONDITIONS. --- 43 unchanged lines hidden (view full) --- 52FaultName MachineCheckFault::_name = "Machine Check"; 53FaultVect MachineCheckFault::_vect = 0x0401; 54FaultStat MachineCheckFault::_count; 55 56FaultName AlignmentFault::_name = "Alignment"; 57FaultVect AlignmentFault::_vect = 0x0301; 58FaultStat AlignmentFault::_count; 59 |
60FaultName ResetFault::_name = "Reset Fault"; |
61#if FULL_SYSTEM 62FaultVect ResetFault::_vect = 0xBFC00000; 63#else 64FaultVect ResetFault::_vect = 0x001; 65#endif 66FaultStat ResetFault::_count; 67 68FaultName AddressErrorFault::_name = "Address Error"; --- 4 unchanged lines hidden (view full) --- 73FaultVect StoreAddressErrorFault::_vect = 0x0180; 74FaultStat StoreAddressErrorFault::_count; 75 76 77FaultName SystemCallFault::_name = "Syscall"; 78FaultVect SystemCallFault::_vect = 0x0180; 79FaultStat SystemCallFault::_count; 80 |
81FaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable Fault"; |
82FaultVect CoprocessorUnusableFault::_vect = 0x180; 83FaultStat CoprocessorUnusableFault::_count; 84 |
85FaultName ReservedInstructionFault::_name = "Reserved Instruction Fault"; |
86FaultVect ReservedInstructionFault::_vect = 0x0180; 87FaultStat ReservedInstructionFault::_count; 88 |
89FaultName ThreadFault::_name = "Thread Fault"; |
90FaultVect ThreadFault::_vect = 0x00F1; 91FaultStat ThreadFault::_count; 92 93 94FaultName ArithmeticFault::_name = "Arithmetic Overflow Exception"; 95FaultVect ArithmeticFault::_vect = 0x180; 96FaultStat ArithmeticFault::_count; 97 --- 356 unchanged lines hidden (view full) --- 454 setHandlerPC(HandlerBase,tc); 455#endif 456} 457 458#endif // FULL_SYSTEM 459 460void ResetFault::invoke(ThreadContext *tc) 461{ |
462#if FULL_SYSTEM |
463 DPRINTF(MipsPRA,"%s encountered.\n", name()); 464 /* All reset activity must be invoked from here */ 465 tc->setPC(vect()); 466 tc->setNextPC(vect()+sizeof(MachInst)); 467 tc->setNextNPC(vect()+sizeof(MachInst)+sizeof(MachInst)); 468 DPRINTF(MipsPRA,"(%x) - ResetFault::invoke : PC set to %x",(unsigned)tc,(unsigned)tc->readPC()); |
469#endif 470 471 // Set Coprocessor 1 (Floating Point) To Usable 472 tc->setMiscReg(MipsISA::Status, MipsISA::Status | 0x20000000); |
473} 474 475void ReservedInstructionFault::invoke(ThreadContext *tc) 476{ 477#if FULL_SYSTEM 478 DPRINTF(MipsPRA,"%s encountered.\n", name()); 479 //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil 480 setExceptionState(tc,0x0A); --- 28 unchanged lines hidden (view full) --- 509 tc->setMiscRegNoEffect(MipsISA::Cause,cause); 510 511 Addr HandlerBase; 512 HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector 513 setHandlerPC(HandlerBase,tc); 514 515 // warn("Status: %x, Cause: %x\n",tc->readMiscReg(MipsISA::Status),tc->readMiscReg(MipsISA::Cause)); 516#else |
517 warn("%s (CP%d) encountered.\n", name(), coProcID); |
518#endif 519} 520 521} // namespace MipsISA 522 |