1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Korey Sewell
31 * Jaidev Patwardhan
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Korey Sewell
31 * Jaidev Patwardhan
|
| 32 * Zhengxing Li
33 * Deyuan Guo
|
32 */
33
34#include "arch/mips/faults.hh"
35#include "arch/mips/pra_constants.hh"
36#include "base/trace.hh"
37#include "cpu/base.hh"
38#include "cpu/thread_context.hh"
39#include "debug/MipsPRA.hh"
40
41#if !FULL_SYSTEM
42#include "mem/page_table.hh"
43#include "sim/process.hh"
44#endif
45
46namespace MipsISA
47{
48
49typedef MipsFaultBase::FaultVals FaultVals;
50
51template <> FaultVals MipsFault<SystemCallFault>::vals =
52 { "Syscall", 0x180, ExcCodeSys };
53
54template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
55 { "Reserved Instruction Fault", 0x180, ExcCodeRI };
56
57template <> FaultVals MipsFault<ThreadFault>::vals =
58 { "Thread Fault", 0x180, ExcCodeDummy };
59
60template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
61 { "Integer Overflow Exception", 0x180, ExcCodeOv };
62
63template <> FaultVals MipsFault<TrapFault>::vals =
64 { "Trap", 0x180, ExcCodeTr };
65
66template <> FaultVals MipsFault<BreakpointFault>::vals =
67 { "Breakpoint", 0x180, ExcCodeBp };
68
69template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
70 { "DSP Disabled Fault", 0x180, ExcCodeDummy };
71
72template <> FaultVals MipsFault<MachineCheckFault>::vals =
73 { "Machine Check", 0x180, ExcCodeMCheck };
74
75template <> FaultVals MipsFault<ResetFault>::vals =
76 { "Reset Fault", 0x000, ExcCodeDummy };
77
78template <> FaultVals MipsFault<SoftResetFault>::vals =
79 { "Soft Reset Fault", 0x000, ExcCodeDummy };
80
81template <> FaultVals MipsFault<NonMaskableInterrupt>::vals =
82 { "Non Maskable Interrupt", 0x000, ExcCodeDummy };
83
84template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
85 { "Coprocessor Unusable Fault", 0x180, ExcCodeCpU };
86
87template <> FaultVals MipsFault<InterruptFault>::vals =
88 { "Interrupt", 0x000, ExcCodeInt };
89
90template <> FaultVals MipsFault<AddressErrorFault>::vals =
91 { "Address Error", 0x180, ExcCodeDummy };
92
93template <> FaultVals MipsFault<TlbInvalidFault>::vals =
94 { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy };
95
96template <> FaultVals MipsFault<TlbRefillFault>::vals =
97 { "TLB Refill Exception", 0x180, ExcCodeDummy };
98
99template <> FaultVals MipsFault<TlbModifiedFault>::vals =
100 { "TLB Modified Exception", 0x180, ExcCodeMod };
101
102void
103MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
104{
105 // modify SRS Ctl - Save CSS, put ESS into CSS
106 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
107 if (status.exl != 1 && status.bev != 1) {
108 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
109 SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
110 srsCtl.pss = srsCtl.css;
111 srsCtl.css = srsCtl.ess;
112 tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
113 }
114
115 // set EXL bit (don't care if it is already set!)
116 status.exl = 1;
117 tc->setMiscRegNoEffect(MISCREG_STATUS, status);
118
119 // write EPC
120 PCState pc = tc->pcState();
121 DPRINTF(MipsPRA, "PC: %s\n", pc);
122 bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
123 tc->setMiscRegNoEffect(MISCREG_EPC,
| 34 */
35
36#include "arch/mips/faults.hh"
37#include "arch/mips/pra_constants.hh"
38#include "base/trace.hh"
39#include "cpu/base.hh"
40#include "cpu/thread_context.hh"
41#include "debug/MipsPRA.hh"
42
43#if !FULL_SYSTEM
44#include "mem/page_table.hh"
45#include "sim/process.hh"
46#endif
47
48namespace MipsISA
49{
50
51typedef MipsFaultBase::FaultVals FaultVals;
52
53template <> FaultVals MipsFault<SystemCallFault>::vals =
54 { "Syscall", 0x180, ExcCodeSys };
55
56template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
57 { "Reserved Instruction Fault", 0x180, ExcCodeRI };
58
59template <> FaultVals MipsFault<ThreadFault>::vals =
60 { "Thread Fault", 0x180, ExcCodeDummy };
61
62template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
63 { "Integer Overflow Exception", 0x180, ExcCodeOv };
64
65template <> FaultVals MipsFault<TrapFault>::vals =
66 { "Trap", 0x180, ExcCodeTr };
67
68template <> FaultVals MipsFault<BreakpointFault>::vals =
69 { "Breakpoint", 0x180, ExcCodeBp };
70
71template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
72 { "DSP Disabled Fault", 0x180, ExcCodeDummy };
73
74template <> FaultVals MipsFault<MachineCheckFault>::vals =
75 { "Machine Check", 0x180, ExcCodeMCheck };
76
77template <> FaultVals MipsFault<ResetFault>::vals =
78 { "Reset Fault", 0x000, ExcCodeDummy };
79
80template <> FaultVals MipsFault<SoftResetFault>::vals =
81 { "Soft Reset Fault", 0x000, ExcCodeDummy };
82
83template <> FaultVals MipsFault<NonMaskableInterrupt>::vals =
84 { "Non Maskable Interrupt", 0x000, ExcCodeDummy };
85
86template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
87 { "Coprocessor Unusable Fault", 0x180, ExcCodeCpU };
88
89template <> FaultVals MipsFault<InterruptFault>::vals =
90 { "Interrupt", 0x000, ExcCodeInt };
91
92template <> FaultVals MipsFault<AddressErrorFault>::vals =
93 { "Address Error", 0x180, ExcCodeDummy };
94
95template <> FaultVals MipsFault<TlbInvalidFault>::vals =
96 { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy };
97
98template <> FaultVals MipsFault<TlbRefillFault>::vals =
99 { "TLB Refill Exception", 0x180, ExcCodeDummy };
100
101template <> FaultVals MipsFault<TlbModifiedFault>::vals =
102 { "TLB Modified Exception", 0x180, ExcCodeMod };
103
104void
105MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
106{
107 // modify SRS Ctl - Save CSS, put ESS into CSS
108 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
109 if (status.exl != 1 && status.bev != 1) {
110 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
111 SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
112 srsCtl.pss = srsCtl.css;
113 srsCtl.css = srsCtl.ess;
114 tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
115 }
116
117 // set EXL bit (don't care if it is already set!)
118 status.exl = 1;
119 tc->setMiscRegNoEffect(MISCREG_STATUS, status);
120
121 // write EPC
122 PCState pc = tc->pcState();
123 DPRINTF(MipsPRA, "PC: %s\n", pc);
124 bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
125 tc->setMiscRegNoEffect(MISCREG_EPC,
|
124 pc.pc() - delay_slot ? sizeof(MachInst) : 0);
| 126 pc.pc() - (delay_slot ? sizeof(MachInst) : 0));
|
125
126 // Set Cause_EXCCODE field
127 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
128 cause.excCode = excCode;
129 cause.bd = delay_slot ? 1 : 0;
130 cause.ce = 0;
131 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
132}
133
134void
135MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
136{
137 if (FULL_SYSTEM) {
138 DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
139 setExceptionState(tc, code());
140 tc->pcState(vect(tc));
141 } else {
142 panic("Fault %s encountered.\n", name());
143 }
144}
145
146void
147ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
148{
149 if (FULL_SYSTEM) {
150 DPRINTF(MipsPRA, "%s encountered.\n", name());
151 /* All reset activity must be invoked from here */
152 Addr handler = vect(tc);
153 tc->pcState(handler);
154 DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler);
155 }
156
157 // Set Coprocessor 1 (Floating Point) To Usable
158 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
159 status.cu.cu1 = 1;
160 tc->setMiscReg(MISCREG_STATUS, status);
161}
162
163void
164SoftResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
165{
166 panic("Soft reset not implemented.\n");
167}
168
169void
170NonMaskableInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
171{
172 panic("Non maskable interrupt not implemented.\n");
173}
174
175} // namespace MipsISA
176
| 127
128 // Set Cause_EXCCODE field
129 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
130 cause.excCode = excCode;
131 cause.bd = delay_slot ? 1 : 0;
132 cause.ce = 0;
133 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
134}
135
136void
137MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
138{
139 if (FULL_SYSTEM) {
140 DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
141 setExceptionState(tc, code());
142 tc->pcState(vect(tc));
143 } else {
144 panic("Fault %s encountered.\n", name());
145 }
146}
147
148void
149ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
150{
151 if (FULL_SYSTEM) {
152 DPRINTF(MipsPRA, "%s encountered.\n", name());
153 /* All reset activity must be invoked from here */
154 Addr handler = vect(tc);
155 tc->pcState(handler);
156 DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler);
157 }
158
159 // Set Coprocessor 1 (Floating Point) To Usable
160 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
161 status.cu.cu1 = 1;
162 tc->setMiscReg(MISCREG_STATUS, status);
163}
164
165void
166SoftResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
167{
168 panic("Soft reset not implemented.\n");
169}
170
171void
172NonMaskableInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
173{
174 panic("Non maskable interrupt not implemented.\n");
175}
176
177} // namespace MipsISA
178
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