1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Korey Sewell
30 */
31
32#include "arch/mips/faults.hh"
33#include "cpu/thread_context.hh"
34#include "cpu/base.hh"
35#include "base/trace.hh"
36
37#if !FULL_SYSTEM
38#include "sim/process.hh"
39#include "mem/page_table.hh"
40#endif
41
42namespace MipsISA
43{
44
45FaultName MachineCheckFault::_name = "Machine Check";
46FaultVect MachineCheckFault::_vect = 0x0401;
47FaultStat MachineCheckFault::_count;
48
49FaultName AlignmentFault::_name = "Alignment";
50FaultVect AlignmentFault::_vect = 0x0301;
51FaultStat AlignmentFault::_count;
52
53FaultName ResetFault::_name = "reset";
54FaultVect ResetFault::_vect = 0x0001;
55FaultStat ResetFault::_count;
56
57FaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable";
58FaultVect CoprocessorUnusableFault::_vect = 0xF001;
59FaultStat CoprocessorUnusableFault::_count;
60
61FaultName ReservedInstructionFault::_name = "Reserved Instruction";
62FaultVect ReservedInstructionFault::_vect = 0x0F01;
63FaultStat ReservedInstructionFault::_count;
64
65FaultName ThreadFault::_name = "thread";
66FaultVect ThreadFault::_vect = 0x00F1;
67FaultStat ThreadFault::_count;
68
69
70FaultName ArithmeticFault::_name = "arith";
71FaultVect ArithmeticFault::_vect = 0x0501;
72FaultStat ArithmeticFault::_count;
73
74FaultName UnimplementedOpcodeFault::_name = "opdec";
75FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
76FaultStat UnimplementedOpcodeFault::_count;
77
78FaultName InterruptFault::_name = "interrupt";
79FaultVect InterruptFault::_vect = 0x0101;
80FaultStat InterruptFault::_count;
81
82FaultName NDtbMissFault::_name = "dtb_miss_single";
83FaultVect NDtbMissFault::_vect = 0x0201;
84FaultStat NDtbMissFault::_count;
85
86FaultName PDtbMissFault::_name = "dtb_miss_double";
87FaultVect PDtbMissFault::_vect = 0x0281;
88FaultStat PDtbMissFault::_count;
89
90FaultName DtbPageFault::_name = "dfault";
91FaultVect DtbPageFault::_vect = 0x0381;
92FaultStat DtbPageFault::_count;
93
94FaultName DtbAcvFault::_name = "dfault";
95FaultVect DtbAcvFault::_vect = 0x0381;
96FaultStat DtbAcvFault::_count;
97
98FaultName ItbMissFault::_name = "itbmiss";
99FaultVect ItbMissFault::_vect = 0x0181;
100FaultStat ItbMissFault::_count;
101
102FaultName ItbPageFault::_name = "itbmiss";
103FaultVect ItbPageFault::_vect = 0x0181;
104FaultStat ItbPageFault::_count;
105
106FaultName ItbAcvFault::_name = "iaccvio";
107FaultVect ItbAcvFault::_vect = 0x0081;
108FaultStat ItbAcvFault::_count;
109
110FaultName FloatEnableFault::_name = "fen";
111FaultVect FloatEnableFault::_vect = 0x0581;
112FaultStat FloatEnableFault::_count;
113
114FaultName IntegerOverflowFault::_name = "intover";
115FaultVect IntegerOverflowFault::_vect = 0x0501;
116FaultStat IntegerOverflowFault::_count;
117
118FaultName DspStateDisabledFault::_name = "intover";
119FaultVect DspStateDisabledFault::_vect = 0x001a;
120FaultStat DspStateDisabledFault::_count;
121
122void ResetFault::invoke(ThreadContext *tc)
123{
124 warn("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
125 //tc->getCpuPtr()->reset();
126}
127
128void CoprocessorUnusableFault::invoke(ThreadContext *tc)
129{
130 panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
131}
132
133void ReservedInstructionFault::invoke(ThreadContext *tc)
134{
135 panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
136}
137
138void ThreadFault::invoke(ThreadContext *tc)
139{
140 panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
141}
142
143void DspStateDisabledFault::invoke(ThreadContext *tc)
144{
145 panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
146}
147
148} // namespace MipsISA
149