1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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27 *
28 * Authors: Korey Sewell
29 */
30
31#include "arch/mips/faults.hh"
32#include "cpu/thread_context.hh"
33#include "cpu/base.hh"
34#include "base/trace.hh"
35
36namespace MipsISA
37{
38
39FaultName MachineCheckFault::_name = "Machine Check";
40FaultVect MachineCheckFault::_vect = 0x0401;
41FaultStat MachineCheckFault::_count;
42

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47FaultName ResetFault::_name = "reset";
48FaultVect ResetFault::_vect = 0x0001;
49FaultStat ResetFault::_count;
50
51FaultName ArithmeticFault::_name = "arith";
52FaultVect ArithmeticFault::_vect = 0x0501;
53FaultStat ArithmeticFault::_count;
54
55FaultName InterruptFault::_name = "interrupt";
56FaultVect InterruptFault::_vect = 0x0101;
57FaultStat InterruptFault::_count;
58
59FaultName NDtbMissFault::_name = "dtb_miss_single";
60FaultVect NDtbMissFault::_vect = 0x0201;
61FaultStat NDtbMissFault::_count;
62

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122}
123
124void ArithmeticFault::invoke(ThreadContext * tc)
125{
126 FaultBase::invoke(tc);
127 panic("Arithmetic traps are unimplemented!");
128}
129
130#endif
131
132} // namespace MipsISA
133