1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 * Korey Sewell
31 * Jaidev Patwardhan
32 * Zhengxing Li
33 * Deyuan Guo
34 */
35
36#include "arch/mips/faults.hh"
37#include "arch/mips/pra_constants.hh"
38#include "base/trace.hh"
39#include "cpu/base.hh"
40#include "cpu/thread_context.hh"
41#include "debug/MipsPRA.hh"
42#include "mem/page_table.hh"
43#include "sim/process.hh"
44
45namespace MipsISA
46{
47
48typedef MipsFaultBase::FaultVals FaultVals;
49
50template <> FaultVals MipsFault<SystemCallFault>::vals =
51 { "Syscall", 0x180, ExcCodeSys };
52
53template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
54 { "Reserved Instruction Fault", 0x180, ExcCodeRI };
55
56template <> FaultVals MipsFault<ThreadFault>::vals =
57 { "Thread Fault", 0x180, ExcCodeDummy };
58
59template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
60 { "Integer Overflow Exception", 0x180, ExcCodeOv };
61
62template <> FaultVals MipsFault<TrapFault>::vals =
63 { "Trap", 0x180, ExcCodeTr };
64
65template <> FaultVals MipsFault<BreakpointFault>::vals =
66 { "Breakpoint", 0x180, ExcCodeBp };
67
68template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
69 { "DSP Disabled Fault", 0x180, ExcCodeDummy };
70
71template <> FaultVals MipsFault<MachineCheckFault>::vals =
72 { "Machine Check", 0x180, ExcCodeMCheck };
73
74template <> FaultVals MipsFault<ResetFault>::vals =
75 { "Reset Fault", 0x000, ExcCodeDummy };
76
77template <> FaultVals MipsFault<SoftResetFault>::vals =
78 { "Soft Reset Fault", 0x000, ExcCodeDummy };
79
80template <> FaultVals MipsFault<NonMaskableInterrupt>::vals =
81 { "Non Maskable Interrupt", 0x000, ExcCodeDummy };
82
83template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
84 { "Coprocessor Unusable Fault", 0x180, ExcCodeCpU };
85
86template <> FaultVals MipsFault<InterruptFault>::vals =
87 { "Interrupt", 0x000, ExcCodeInt };
88
89template <> FaultVals MipsFault<AddressErrorFault>::vals =
90 { "Address Error", 0x180, ExcCodeDummy };
91
92template <> FaultVals MipsFault<TlbInvalidFault>::vals =
93 { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy };
94
95template <> FaultVals MipsFault<TlbRefillFault>::vals =
96 { "TLB Refill Exception", 0x180, ExcCodeDummy };
97
98template <> MipsFaultBase::FaultVals MipsFault<TlbModifiedFault>::vals =
99 { "TLB Modified Exception", 0x180, ExcCodeMod };
100
101void
102MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
103{
104 // modify SRS Ctl - Save CSS, put ESS into CSS
105 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
106 if (status.exl != 1 && status.bev != 1) {
107 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
108 SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
109 srsCtl.pss = srsCtl.css;
110 srsCtl.css = srsCtl.ess;
111 tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
112 }
113
114 // set EXL bit (don't care if it is already set!)
115 status.exl = 1;
116 tc->setMiscRegNoEffect(MISCREG_STATUS, status);
117
118 // write EPC
119 PCState pc = tc->pcState();
120 DPRINTF(MipsPRA, "PC: %s\n", pc);
121 bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
122 tc->setMiscRegNoEffect(MISCREG_EPC,
123 pc.pc() - (delay_slot ? sizeof(MachInst) : 0));
124
125 // Set Cause_EXCCODE field
126 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
127 cause.excCode = excCode;
128 cause.bd = delay_slot ? 1 : 0;
129 cause.ce = 0;
130 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
131}
132
133void
134MipsFaultBase::invoke(ThreadContext *tc, const StaticInstPtr &inst)
135{
136 if (FullSystem) {
137 DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
138 setExceptionState(tc, code());
139 tc->pcState(vect(tc));
140 } else {
141 panic("Fault %s encountered.\n", name());
142 }
143}
144
145void
146ResetFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
147{
148 if (FullSystem) {
149 DPRINTF(MipsPRA, "%s encountered.\n", name());
150 /* All reset activity must be invoked from here */
151 Addr handler = vect(tc);
152 tc->pcState(handler);
153 DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", handler);
154 }
155
156 // Set Coprocessor 1 (Floating Point) To Usable
157 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
158 status.cu.cu1 = 1;
159 tc->setMiscReg(MISCREG_STATUS, status);
160}
161
162void
163SoftResetFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
164{
165 panic("Soft reset not implemented.\n");
166}
167
168void
169NonMaskableInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
170{
171 panic("Non maskable interrupt not implemented.\n");
172}
173
174} // namespace MipsISA
175