1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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46namespace MipsISA
47{
48
49typedef MipsFaultBase::FaultVals FaultVals;
50
51template <> FaultVals MipsFault<MachineCheckFault>::vals =
52 { "Machine Check", 0x0401 };
53
54template <> FaultVals MipsFault<ResetFault>::vals =
55#if FULL_SYSTEM
56 { "Reset Fault", 0xBFC00000};
57#else
58 { "Reset Fault", 0x001};
59#endif
60
61template <> FaultVals MipsFault<AddressErrorFault>::vals =

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71 { "Coprocessor Unusable Fault", 0x180 };
72
73template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
74 { "Reserved Instruction Fault", 0x0180 };
75
76template <> FaultVals MipsFault<ThreadFault>::vals =
77 { "Thread Fault", 0x00F1 };
78
79template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
80 { "Integer Overflow Exception", 0x180 };
81
82template <> FaultVals MipsFault<InterruptFault>::vals =
83 { "interrupt", 0x0180 };
84
85template <> FaultVals MipsFault<TrapFault>::vals =
86 { "Trap", 0x0180 };
87
88template <> FaultVals MipsFault<BreakpointFault>::vals =
89 { "Breakpoint", 0x0180 };
90
91template <> FaultVals MipsFault<ItbInvalidFault>::vals =
92 { "Invalid TLB Entry Exception (I-Fetch/LW)", 0x0180 };
93
94template <> FaultVals MipsFault<ItbRefillFault>::vals =
95 { "TLB Refill Exception (I-Fetch/LW)", 0x0180 };
96
97template <> FaultVals MipsFault<DtbInvalidFault>::vals =
98 { "Invalid TLB Entry Exception (Store)", 0x0180 };
99
100template <> FaultVals MipsFault<DtbRefillFault>::vals =
101 { "TLB Refill Exception (Store)", 0x0180 };
102
103template <> FaultVals MipsFault<TLBModifiedFault>::vals =
104 { "TLB Modified Exception", 0x0180 };
105
106template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
107 { "DSP Disabled Fault", 0x001a };
108
109#if FULL_SYSTEM
110void
111MipsFaultBase::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
112{
113 tc->setPC(HandlerBase);

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152 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
153 cause.excCode = excCode;
154 cause.bd = bd;
155 cause.ce = 0;
156 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
157}
158
159void
160IntegerOverflowFault::invoke(ThreadContext *tc, StaticInstPtr inst)
161{
162 DPRINTF(MipsPRA, "%s encountered.\n", name());
163 setExceptionState(tc, 0xC);
164
165 // Set new PC
166 Addr HandlerBase;
167 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
168 // Here, the handler is dependent on BEV, which is not modified by

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