dsp.hh (5268:5bfc53fe60e7) dsp.hh (5558:cb98f0fcc6c6)
1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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36#include "base/misc.hh"
37#include "config/full_system.hh"
38#include "sim/host.hh"
39
40class ThreadContext;
41
42namespace MipsISA {
43
1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 27 unchanged lines hidden (view full) ---

36#include "base/misc.hh"
37#include "config/full_system.hh"
38#include "sim/host.hh"
39
40class ThreadContext;
41
42namespace MipsISA {
43
44 // SIMD formats
45 enum {
46 SIMD_FMT_L, // long word
47 SIMD_FMT_W, // word
48 SIMD_FMT_PH, // paired halfword
49 SIMD_FMT_QB, // quad byte
50 SIMD_NUM_FMTS
51 };
44// SIMD formats
45enum {
46 SIMD_FMT_L, // long word
47 SIMD_FMT_W, // word
48 SIMD_FMT_PH, // paired halfword
49 SIMD_FMT_QB, // quad byte
50 SIMD_NUM_FMTS
51};
52
52
53 // DSPControl Fields
54 enum {
55 DSP_POS, // insertion bitfield position
56 DSP_SCOUNT, // insertion bitfield size
57 DSP_C, // carry bit
58 DSP_OUFLAG, // overflow-underflow flag
59 DSP_CCOND, // condition code
60 DSP_EFI, // extract fail indicator bit
61 DSP_NUM_FIELDS
62 };
53// DSPControl Fields
54enum {
55 DSP_POS, // insertion bitfield position
56 DSP_SCOUNT, // insertion bitfield size
57 DSP_C, // carry bit
58 DSP_OUFLAG, // overflow-underflow flag
59 DSP_CCOND, // condition code
60 DSP_EFI, // extract fail indicator bit
61 DSP_NUM_FIELDS
62};
63
63
64 // compare instruction operations
65 enum {
66 CMP_EQ, // equal
67 CMP_LT, // less than
68 CMP_LE // less than or equal
69 };
64// compare instruction operations
65enum {
66 CMP_EQ, // equal
67 CMP_LT, // less than
68 CMP_LE // less than or equal
69};
70
70
71 // SIMD operation order modes
72 enum {
73 MODE_L, // left
74 MODE_R, // right
75 MODE_LA, // left-alternate
76 MODE_RA, // right-alternate
77 MODE_X // cross
78 };
71// SIMD operation order modes
72enum {
73 MODE_L, // left
74 MODE_R, // right
75 MODE_LA, // left-alternate
76 MODE_RA, // right-alternate
77 MODE_X // cross
78};
79
79
80 // dsp operation parameters
81 enum { UNSIGNED, SIGNED };
82 enum { NOSATURATE, SATURATE };
83 enum { NOROUND, ROUND };
80// dsp operation parameters
81enum { UNSIGNED, SIGNED };
82enum { NOSATURATE, SATURATE };
83enum { NOROUND, ROUND };
84
84
85 // DSPControl field positions and masks
86 const uint32_t DSP_CTL_POS[DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 };
87 const uint32_t DSP_CTL_MASK[DSP_NUM_FIELDS] = { 0x0000003f, 0x00001f80, 0x00002000,
88 0x00ff0000, 0x0f000000, 0x00004000 };
85// DSPControl field positions and masks
86const uint32_t DSP_CTL_POS[DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 };
87const uint32_t DSP_CTL_MASK[DSP_NUM_FIELDS] =
88{ 0x0000003f, 0x00001f80, 0x00002000,
89 0x00ff0000, 0x0f000000, 0x00004000 };
89
90
90 // SIMD format constants
91 const uint32_t SIMD_MAX_VALS = 4; // maximum values per register
92 const uint32_t SIMD_NVALS[SIMD_NUM_FMTS] = { 1, 1, 2, 4 }; // number of values in fmt
93 const uint32_t SIMD_NBITS[SIMD_NUM_FMTS] = { 64, 32, 16, 8 }; // number of bits per value
94 const uint32_t SIMD_LOG2N[SIMD_NUM_FMTS] = { 6, 5, 4, 3 }; // log2( bits per value )
91/*
92 * SIMD format constants
93 */
95
94
96 // DSP maximum values
97 const uint64_t FIXED_L_SMAX = ULL(0x7fffffffffffffff);
98 const uint64_t FIXED_W_SMAX = ULL(0x000000007fffffff);
99 const uint64_t FIXED_H_SMAX = ULL(0x0000000000007fff);
100 const uint64_t FIXED_B_SMAX = ULL(0x000000000000007f);
101 const uint64_t FIXED_L_UMAX = ULL(0xffffffffffffffff);
102 const uint64_t FIXED_W_UMAX = ULL(0x00000000ffffffff);
103 const uint64_t FIXED_H_UMAX = ULL(0x000000000000ffff);
104 const uint64_t FIXED_B_UMAX = ULL(0x00000000000000ff);
105 const uint64_t FIXED_SMAX[SIMD_NUM_FMTS] = { FIXED_L_SMAX, FIXED_W_SMAX, FIXED_H_SMAX, FIXED_B_SMAX };
106 const uint64_t FIXED_UMAX[SIMD_NUM_FMTS] = { FIXED_L_UMAX, FIXED_W_UMAX, FIXED_H_UMAX, FIXED_B_UMAX };
95// maximum values per register
96const uint32_t SIMD_MAX_VALS = 4;
97// number of values in fmt
98const uint32_t SIMD_NVALS[SIMD_NUM_FMTS] = { 1, 1, 2, 4 };
99// number of bits per value
100const uint32_t SIMD_NBITS[SIMD_NUM_FMTS] = { 64, 32, 16, 8 };
101// log2(bits per value)
102const uint32_t SIMD_LOG2N[SIMD_NUM_FMTS] = { 6, 5, 4, 3 };
107
103
108 // DSP minimum values
109 const uint64_t FIXED_L_SMIN = ULL(0x8000000000000000);
110 const uint64_t FIXED_W_SMIN = ULL(0xffffffff80000000);
111 const uint64_t FIXED_H_SMIN = ULL(0xffffffffffff8000);
112 const uint64_t FIXED_B_SMIN = ULL(0xffffffffffffff80);
113 const uint64_t FIXED_L_UMIN = ULL(0x0000000000000000);
114 const uint64_t FIXED_W_UMIN = ULL(0x0000000000000000);
115 const uint64_t FIXED_H_UMIN = ULL(0x0000000000000000);
116 const uint64_t FIXED_B_UMIN = ULL(0x0000000000000000);
117 const uint64_t FIXED_SMIN[SIMD_NUM_FMTS] = { FIXED_L_SMIN, FIXED_W_SMIN, FIXED_H_SMIN, FIXED_B_SMIN };
118 const uint64_t FIXED_UMIN[SIMD_NUM_FMTS] = { FIXED_L_UMIN, FIXED_W_UMIN, FIXED_H_UMIN, FIXED_B_UMIN };
119
104
120 // DSP utility functions
121 int32_t bitrev( int32_t value );
122 uint64_t dspSaturate( uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow );
123 uint64_t checkOverflow( uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow );
124 uint64_t signExtend( uint64_t value, int32_t signpos );
125 uint64_t addHalfLsb( uint64_t value, int32_t lsbpos );
126 int32_t dspAbs( int32_t a, int32_t fmt, uint32_t *dspctl );
127 int32_t dspAdd( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl );
128 int32_t dspAddh( int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign );
129 int32_t dspSub( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl );
130 int32_t dspSubh( int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign );
131 int32_t dspShll( int32_t a, uint32_t sa, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl );
132 int32_t dspShrl( int32_t a, uint32_t sa, int32_t fmt, int32_t sign );
133 int32_t dspShra( int32_t a, uint32_t sa, int32_t fmt, int32_t round, int32_t sign, uint32_t *dspctl );
134 int32_t dspMul( int32_t a, int32_t b, int32_t fmt, int32_t saturate, uint32_t *dspctl );
135 int32_t dspMulq( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t round, uint32_t *dspctl );
136 int32_t dspMuleu( int32_t a, int32_t b, int32_t mode, uint32_t *dspctl );
137 int32_t dspMuleq( int32_t a, int32_t b, int32_t mode, uint32_t *dspctl );
138 int64_t dspDpaq( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt,
139 int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl );
140 int64_t dspDpsq( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt,
141 int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl );
142 int64_t dspDpa( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode );
143 int64_t dspDps( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode );
144 int64_t dspMaq( int64_t dspac, int32_t a, int32_t b, int32_t ac,
145 int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl );
146 int64_t dspMulsa( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt );
147 int64_t dspMulsaq( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, uint32_t *dspctl );
148 void dspCmp( int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl );
149 int32_t dspCmpg( int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op );
150 int32_t dspCmpgd( int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl );
151 int32_t dspPrece( int32_t a, int32_t infmt, int32_t insign, int32_t outfmt, int32_t outsign, int32_t mode );
152 int32_t dspPrecrqu( int32_t a, int32_t b, uint32_t *dspctl );
153 int32_t dspPrecrq( int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl );
154 int32_t dspPrecrSra( int32_t a, int32_t b, int32_t sa, int32_t fmt, int32_t round );
155 int32_t dspPick( int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl );
156 int32_t dspPack( int32_t a, int32_t b, int32_t fmt );
157 int32_t dspExtr( int64_t dspac, int32_t fmt, int32_t sa, int32_t round,
158 int32_t saturate, uint32_t *dspctl );
159 int32_t dspExtp( int64_t dspac, int32_t size, uint32_t *dspctl );
160 int32_t dspExtpd( int64_t dspac, int32_t size, uint32_t *dspctl );
105// DSP maximum values
106const uint64_t FIXED_L_SMAX = ULL(0x7fffffffffffffff);
107const uint64_t FIXED_W_SMAX = ULL(0x000000007fffffff);
108const uint64_t FIXED_H_SMAX = ULL(0x0000000000007fff);
109const uint64_t FIXED_B_SMAX = ULL(0x000000000000007f);
110const uint64_t FIXED_L_UMAX = ULL(0xffffffffffffffff);
111const uint64_t FIXED_W_UMAX = ULL(0x00000000ffffffff);
112const uint64_t FIXED_H_UMAX = ULL(0x000000000000ffff);
113const uint64_t FIXED_B_UMAX = ULL(0x00000000000000ff);
114const uint64_t FIXED_SMAX[SIMD_NUM_FMTS] =
115{ FIXED_L_SMAX, FIXED_W_SMAX, FIXED_H_SMAX, FIXED_B_SMAX };
116const uint64_t FIXED_UMAX[SIMD_NUM_FMTS] =
117{ FIXED_L_UMAX, FIXED_W_UMAX, FIXED_H_UMAX, FIXED_B_UMAX };
161
118
162 // SIMD pack/unpack utility functions
163 void simdPack( uint64_t *values_ptr, int32_t *reg, int32_t fmt );
164 void simdUnpack( int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign );
119// DSP minimum values
120const uint64_t FIXED_L_SMIN = ULL(0x8000000000000000);
121const uint64_t FIXED_W_SMIN = ULL(0xffffffff80000000);
122const uint64_t FIXED_H_SMIN = ULL(0xffffffffffff8000);
123const uint64_t FIXED_B_SMIN = ULL(0xffffffffffffff80);
124const uint64_t FIXED_L_UMIN = ULL(0x0000000000000000);
125const uint64_t FIXED_W_UMIN = ULL(0x0000000000000000);
126const uint64_t FIXED_H_UMIN = ULL(0x0000000000000000);
127const uint64_t FIXED_B_UMIN = ULL(0x0000000000000000);
128const uint64_t FIXED_SMIN[SIMD_NUM_FMTS] =
129{ FIXED_L_SMIN, FIXED_W_SMIN, FIXED_H_SMIN, FIXED_B_SMIN };
130const uint64_t FIXED_UMIN[SIMD_NUM_FMTS] =
131{ FIXED_L_UMIN, FIXED_W_UMIN, FIXED_H_UMIN, FIXED_B_UMIN };
165
132
166 // DSPControl r/w utility functions
167 void writeDSPControl( uint32_t *dspctl, uint32_t value, uint32_t mask );
168 uint32_t readDSPControl( uint32_t *dspctl, uint32_t mask );
169};
133// DSP utility functions
134int32_t bitrev(int32_t value);
135uint64_t dspSaturate(uint64_t value, int32_t fmt, int32_t sign,
136 uint32_t *overflow);
137uint64_t checkOverflow(uint64_t value, int32_t fmt, int32_t sign,
138 uint32_t *overflow);
139uint64_t signExtend(uint64_t value, int32_t signpos);
140uint64_t addHalfLsb(uint64_t value, int32_t lsbpos);
141int32_t dspAbs(int32_t a, int32_t fmt, uint32_t *dspctl);
142int32_t dspAdd(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
143 int32_t sign, uint32_t *dspctl);
144int32_t dspAddh(int32_t a, int32_t b, int32_t fmt, int32_t round,
145 int32_t sign);
146int32_t dspSub(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
147 int32_t sign, uint32_t *dspctl);
148int32_t dspSubh(int32_t a, int32_t b, int32_t fmt, int32_t round,
149 int32_t sign);
150int32_t dspShll(int32_t a, uint32_t sa, int32_t fmt, int32_t saturate,
151 int32_t sign, uint32_t *dspctl);
152int32_t dspShrl(int32_t a, uint32_t sa, int32_t fmt, int32_t sign);
153int32_t dspShra(int32_t a, uint32_t sa, int32_t fmt, int32_t round,
154 int32_t sign, uint32_t *dspctl);
155int32_t dspMul(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
156 uint32_t *dspctl);
157int32_t dspMulq(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
158 int32_t round, uint32_t *dspctl);
159int32_t dspMuleu(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl);
160int32_t dspMuleq(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl);
161int64_t dspDpaq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
162 int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode,
163 uint32_t *dspctl);
164int64_t dspDpsq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
165 int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode,
166 uint32_t *dspctl);
167int64_t dspDpa(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt,
168 int32_t sign, int32_t mode);
169int64_t dspDps(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt,
170 int32_t sign, int32_t mode);
171int64_t dspMaq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
172 int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl);
173int64_t dspMulsa(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt);
174int64_t dspMulsaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt,
175 uint32_t *dspctl);
176void dspCmp(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op,
177 uint32_t *dspctl);
178int32_t dspCmpg(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op);
179int32_t dspCmpgd(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op,
180 uint32_t *dspctl);
181int32_t dspPrece(int32_t a, int32_t infmt, int32_t insign, int32_t outfmt,
182 int32_t outsign, int32_t mode);
183int32_t dspPrecrqu(int32_t a, int32_t b, uint32_t *dspctl);
184int32_t dspPrecrq(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl);
185int32_t dspPrecrSra(int32_t a, int32_t b, int32_t sa, int32_t fmt,
186 int32_t round);
187int32_t dspPick(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl);
188int32_t dspPack(int32_t a, int32_t b, int32_t fmt);
189int32_t dspExtr(int64_t dspac, int32_t fmt, int32_t sa, int32_t round,
190 int32_t saturate, uint32_t *dspctl);
191int32_t dspExtp(int64_t dspac, int32_t size, uint32_t *dspctl);
192int32_t dspExtpd(int64_t dspac, int32_t size, uint32_t *dspctl);
170
193
171#endif
194// SIMD pack/unpack utility functions
195void simdPack(uint64_t *values_ptr, int32_t *reg, int32_t fmt);
196void simdUnpack(int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign);
197
198// DSPControl r/w utility functions
199void writeDSPControl(uint32_t *dspctl, uint32_t value, uint32_t mask);
200uint32_t readDSPControl(uint32_t *dspctl, uint32_t mask);
201
202} /* namespace MipsISA */
203
204#endif // __ARCH_MIPS_DSP_HH__