SConscript (5192:582e583f8e7e) | SConscript (5222:bb733a878f85) |
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1# -*- mode:python -*- 2 | 1# -*- mode:python -*- 2 |
3# Copyright (c) 2004-2005 The Regents of The University of Michigan | 3# Copyright (c) 2007 MIPS Technologies, Inc. |
4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright 9# notice, this list of conditions and the following disclaimer; 10# redistributions in binary form must reproduce the above copyright 11# notice, this list of conditions and the following disclaimer in the --- 16 unchanged lines hidden (view full) --- 28# 29# Authors: Gabe Black 30# Steve Reinhardt 31# Korey Sewell 32 33Import('*') 34 35if env['TARGET_ISA'] == 'mips': | 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright 9# notice, this list of conditions and the following disclaimer; 10# redistributions in binary form must reproduce the above copyright 11# notice, this list of conditions and the following disclaimer in the --- 16 unchanged lines hidden (view full) --- 28# 29# Authors: Gabe Black 30# Steve Reinhardt 31# Korey Sewell 32 33Import('*') 34 35if env['TARGET_ISA'] == 'mips': |
36 Source('dsp.cc') | |
37 Source('faults.cc') 38 Source('regfile/int_regfile.cc') | 36 Source('faults.cc') 37 Source('regfile/int_regfile.cc') |
38 Source('regfile/float_regfile.cc') |
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39 Source('regfile/misc_regfile.cc') 40 Source('regfile/regfile.cc') 41 Source('tlb.cc') | 39 Source('regfile/misc_regfile.cc') 40 Source('regfile/regfile.cc') 41 Source('tlb.cc') |
42 Source('pagetable.cc') |
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42 Source('utility.cc') | 43 Source('utility.cc') |
44 Source('dsp.cc') |
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43 44 SimObject('MipsTLB.py') | 45 46 SimObject('MipsTLB.py') |
45 | |
46 TraceFlag('MipsPRA') 47 48 if env['FULL_SYSTEM']: | 47 TraceFlag('MipsPRA') 48 49 if env['FULL_SYSTEM']: |
49 #Insert Full-System Files Here 50 pass | 50 SimObject('MipsSystem.py') 51 Source('idle_event.cc') 52 Source('mips_core_specific.cc') 53 Source('vtophys.cc') 54 Source('system.cc') 55 Source('stacktrace.cc') 56 Source('linux/system.cc') 57 Source('interrupts.cc') 58 Source('bare_iron/system.cc') |
51 else: 52 Source('process.cc') | 59 else: 60 Source('process.cc') |
53 | |
54 Source('linux/linux.cc') 55 Source('linux/process.cc') 56 57 # Add in files generated by the ISA description. 58 isa_desc_files = env.ISADesc('isa/main.isa') 59 # Only non-header files need to be compiled. 60 for f in isa_desc_files: 61 if not f.path.endswith('.hh'): 62 Source(f) | 61 Source('linux/linux.cc') 62 Source('linux/process.cc') 63 64 # Add in files generated by the ISA description. 65 isa_desc_files = env.ISADesc('isa/main.isa') 66 # Only non-header files need to be compiled. 67 for f in isa_desc_files: 68 if not f.path.endswith('.hh'): 69 Source(f) |