isa_parser.py (9918:2c7219e2d999) isa_parser.py (9920:028e4da64b42)
1# Copyright (c) 2003-2005 The Regents of The University of Michigan
1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# Copyright (c) 2013 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the

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492 return 0
493
494 def isFloatReg(self):
495 return 0
496
497 def isIntReg(self):
498 return 0
499
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the

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493 return 0
494
495 def isFloatReg(self):
496 return 0
497
498 def isIntReg(self):
499 return 0
500
501 def isCCReg(self):
502 return 0
503
500 def isControlReg(self):
501 return 0
502
503 def isPCState(self):
504 return 0
505
506 def isPCPart(self):
507 return self.isPCState() and self.reg_spec

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655 wb = '''
656 {
657 %s final_val = %s;
658 %s\n
659 if (traceData) { traceData->setData(final_val); }
660 }''' % (self.ctype, self.base_name, wp)
661 return wb
662
504 def isControlReg(self):
505 return 0
506
507 def isPCState(self):
508 return 0
509
510 def isPCPart(self):
511 return self.isPCState() and self.reg_spec

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659 wb = '''
660 {
661 %s final_val = %s;
662 %s\n
663 if (traceData) { traceData->setData(final_val); }
664 }''' % (self.ctype, self.base_name, wp)
665 return wb
666
667class CCRegOperand(Operand):
668 def isReg(self):
669 return 1
670
671 def isCCReg(self):
672 return 1
673
674 def makeConstructor(self, predRead, predWrite):
675 c_src = ''
676 c_dest = ''
677
678 if self.is_src:
679 c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + CC_Reg_Base;' % \
680 (self.reg_spec)
681 if self.hasReadPred():
682 c_src = '\n\tif (%s) {%s\n\t}' % \
683 (self.read_predicate, c_src)
684
685 if self.is_dest:
686 c_dest = \
687 '\n\t_destRegIdx[_numDestRegs++] = %s + CC_Reg_Base;' % \
688 (self.reg_spec)
689 c_dest += '\n\t_numCCDestRegs++;'
690 if self.hasWritePred():
691 c_dest = '\n\tif (%s) {%s\n\t}' % \
692 (self.write_predicate, c_dest)
693
694 return c_src + c_dest
695
696 def makeRead(self, predRead):
697 if (self.ctype == 'float' or self.ctype == 'double'):
698 error('Attempt to read condition-code register as FP')
699 if self.read_code != None:
700 return self.buildReadCode('readCCRegOperand')
701
702 int_reg_val = ''
703 if predRead:
704 int_reg_val = 'xc->readCCRegOperand(this, _sourceIndex++)'
705 if self.hasReadPred():
706 int_reg_val = '(%s) ? %s : 0' % \
707 (self.read_predicate, int_reg_val)
708 else:
709 int_reg_val = 'xc->readCCRegOperand(this, %d)' % self.src_reg_idx
710
711 return '%s = %s;\n' % (self.base_name, int_reg_val)
712
713 def makeWrite(self, predWrite):
714 if (self.ctype == 'float' or self.ctype == 'double'):
715 error('Attempt to write condition-code register as FP')
716 if self.write_code != None:
717 return self.buildWriteCode('setCCRegOperand')
718
719 if predWrite:
720 wp = 'true'
721 if self.hasWritePred():
722 wp = self.write_predicate
723
724 wcond = 'if (%s)' % (wp)
725 windex = '_destIndex++'
726 else:
727 wcond = ''
728 windex = '%d' % self.dest_reg_idx
729
730 wb = '''
731 %s
732 {
733 %s final_val = %s;
734 xc->setCCRegOperand(this, %s, final_val);\n
735 if (traceData) { traceData->setData(final_val); }
736 }''' % (wcond, self.ctype, self.base_name, windex)
737
738 return wb
739
663class ControlRegOperand(Operand):
664 def isReg(self):
665 return 1
666
667 def isControlReg(self):
668 return 1
669
670 def makeConstructor(self, predRead, predWrite):

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810 next_pos = match.end()
811 self.sort()
812 # enumerate source & dest register operands... used in building
813 # constructor later
814 self.numSrcRegs = 0
815 self.numDestRegs = 0
816 self.numFPDestRegs = 0
817 self.numIntDestRegs = 0
740class ControlRegOperand(Operand):
741 def isReg(self):
742 return 1
743
744 def isControlReg(self):
745 return 1
746
747 def makeConstructor(self, predRead, predWrite):

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887 next_pos = match.end()
888 self.sort()
889 # enumerate source & dest register operands... used in building
890 # constructor later
891 self.numSrcRegs = 0
892 self.numDestRegs = 0
893 self.numFPDestRegs = 0
894 self.numIntDestRegs = 0
895 self.numCCDestRegs = 0
818 self.numMiscDestRegs = 0
819 self.memOperand = None
820
821 # Flags to keep track if one or more operands are to be read/written
822 # conditionally.
823 self.predRead = False
824 self.predWrite = False
825

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830 self.numSrcRegs += 1
831 if op_desc.is_dest:
832 op_desc.dest_reg_idx = self.numDestRegs
833 self.numDestRegs += 1
834 if op_desc.isFloatReg():
835 self.numFPDestRegs += 1
836 elif op_desc.isIntReg():
837 self.numIntDestRegs += 1
896 self.numMiscDestRegs = 0
897 self.memOperand = None
898
899 # Flags to keep track if one or more operands are to be read/written
900 # conditionally.
901 self.predRead = False
902 self.predWrite = False
903

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908 self.numSrcRegs += 1
909 if op_desc.is_dest:
910 op_desc.dest_reg_idx = self.numDestRegs
911 self.numDestRegs += 1
912 if op_desc.isFloatReg():
913 self.numFPDestRegs += 1
914 elif op_desc.isIntReg():
915 self.numIntDestRegs += 1
916 elif op_desc.isCCReg():
917 self.numCCDestRegs += 1
838 elif op_desc.isControlReg():
839 self.numMiscDestRegs += 1
840 elif op_desc.isMem():
841 if self.memOperand:
842 error("Code block has more than one memory operand.")
843 self.memOperand = op_desc
844
845 # Check if this operand has read/write predication. If true, then

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1025
1026 # The header of the constructor declares the variables to be used
1027 # in the body of the constructor.
1028 header = ''
1029 header += '\n\t_numSrcRegs = 0;'
1030 header += '\n\t_numDestRegs = 0;'
1031 header += '\n\t_numFPDestRegs = 0;'
1032 header += '\n\t_numIntDestRegs = 0;'
918 elif op_desc.isControlReg():
919 self.numMiscDestRegs += 1
920 elif op_desc.isMem():
921 if self.memOperand:
922 error("Code block has more than one memory operand.")
923 self.memOperand = op_desc
924
925 # Check if this operand has read/write predication. If true, then

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1105
1106 # The header of the constructor declares the variables to be used
1107 # in the body of the constructor.
1108 header = ''
1109 header += '\n\t_numSrcRegs = 0;'
1110 header += '\n\t_numDestRegs = 0;'
1111 header += '\n\t_numFPDestRegs = 0;'
1112 header += '\n\t_numIntDestRegs = 0;'
1113 header += '\n\t_numCCDestRegs = 0;'
1033
1034 self.constructor = header + \
1035 self.operands.concatAttrStrings('constructor')
1036
1037 self.flags = self.operands.concatAttrLists('flags')
1038
1039 # Make a basic guess on the operand class (function unit type).
1040 # These are good enough for most cases, and can be overridden

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1115 self.constructor = header + \
1116 self.operands.concatAttrStrings('constructor')
1117
1118 self.flags = self.operands.concatAttrLists('flags')
1119
1120 # Make a basic guess on the operand class (function unit type).
1121 # These are good enough for most cases, and can be overridden

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