isa_parser.py (6338:14572c7334b5) isa_parser.py (6377:aac74ffc8ca2)
1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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1426 if self.write_code != None:
1427 return self.buildWriteCode('setMiscRegOperand')
1428 wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
1429 (self.dest_reg_idx, self.base_name)
1430 wb += 'if (traceData) { traceData->setData(%s); }' % \
1431 self.base_name
1432 return wb
1433
1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 1417 unchanged lines hidden (view full) ---

1426 if self.write_code != None:
1427 return self.buildWriteCode('setMiscRegOperand')
1428 wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
1429 (self.dest_reg_idx, self.base_name)
1430 wb += 'if (traceData) { traceData->setData(%s); }' % \
1431 self.base_name
1432 return wb
1433
1434class ControlBitfieldOperand(ControlRegOperand):
1435 def makeRead(self):
1436 bit_select = 0
1437 if (self.ctype == 'float' or self.ctype == 'double'):
1438 error(0, 'Attempt to read control register as FP')
1439 if self.read_code != None:
1440 return self.buildReadCode('readMiscReg')
1441 base = 'xc->readMiscReg(%s)' % self.reg_spec
1442 name = self.base_name
1443 return '%s = bits(%s, %s_HI, %s_LO);' % \
1444 (name, base, name, name)
1445
1446 def makeWrite(self):
1447 if (self.ctype == 'float' or self.ctype == 'double'):
1448 error(0, 'Attempt to write control register as FP')
1449 if self.write_code != None:
1450 return self.buildWriteCode('setMiscReg')
1451 base = 'xc->readMiscReg(%s)' % self.reg_spec
1452 name = self.base_name
1453 wb_val = 'insertBits(%s, %s_HI, %s_LO, %s)' % \
1454 (base, name, name, self.base_name)
1455 wb = 'xc->setMiscRegOperand(this, %s, %s );\n' % (self.dest_reg_idx, wb_val)
1456 wb += 'if (traceData) { traceData->setData(%s); }' % \
1457 self.base_name
1458 return wb
1459
1460class MemOperand(Operand):
1461 def isMem(self):
1462 return 1
1463
1464 def makeConstructor(self):
1465 return ''
1466
1467 def makeDecl(self):

--- 587 unchanged lines hidden --- 		1434class MemOperand(Operand):
1435 def isMem(self):
1436 return 1
1437
1438 def makeConstructor(self):
1439 return ''
1440
1441 def makeDecl(self):

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