isa_parser.py (6314:781969fbeca9) isa_parser.py (6338:14572c7334b5)
1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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1262 return 0
1263
1264 def isIntReg(self):
1265 return 0
1266
1267 def isControlReg(self):
1268 return 0
1269
1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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1262 return 0
1263
1264 def isIntReg(self):
1265 return 0
1266
1267 def isControlReg(self):
1268 return 0
1269
1270 def isIControlReg(self):
1271 return 0
1272
1273 def getFlags(self):
1274 # note the empty slice '[:]' gives us a copy of self.flags[0]
1275 # instead of a reference to it
1276 my_flags = self.flags[0][:]
1277 if self.is_src:
1278 my_flags += self.flags[1]
1279 if self.is_dest:
1280 my_flags += self.flags[2]

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1429 if self.write_code != None:
1430 return self.buildWriteCode('setMiscRegOperand')
1431 wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
1432 (self.dest_reg_idx, self.base_name)
1433 wb += 'if (traceData) { traceData->setData(%s); }' % \
1434 self.base_name
1435 return wb
1436
1270 def getFlags(self):
1271 # note the empty slice '[:]' gives us a copy of self.flags[0]
1272 # instead of a reference to it
1273 my_flags = self.flags[0][:]
1274 if self.is_src:
1275 my_flags += self.flags[1]
1276 if self.is_dest:
1277 my_flags += self.flags[2]

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1426 if self.write_code != None:
1427 return self.buildWriteCode('setMiscRegOperand')
1428 wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
1429 (self.dest_reg_idx, self.base_name)
1430 wb += 'if (traceData) { traceData->setData(%s); }' % \
1431 self.base_name
1432 return wb
1433
1437class IControlRegOperand(Operand):
1438 def isReg(self):
1439 return 1
1440
1441 def isIControlReg(self):
1442 return 1
1443
1444 def makeConstructor(self):
1445 c = ''
1446 if self.is_src:
1447 c += '\n\t_srcRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
1448 (self.src_reg_idx, self.reg_spec)
1449 if self.is_dest:
1450 c += '\n\t_destRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
1451 (self.dest_reg_idx, self.reg_spec)
1452 return c
1453
1454 def makeRead(self):
1455 bit_select = 0
1456 if (self.ctype == 'float' or self.ctype == 'double'):
1457 error(0, 'Attempt to read control register as FP')
1458 if self.read_code != None:
1459 return self.buildReadCode('readMiscReg')
1460 base = 'xc->readMiscReg(%s)' % self.reg_spec
1461 if self.size == self.dflt_size:
1462 return '%s = %s;\n' % (self.base_name, base)
1463 else:
1464 return '%s = bits(%s, %d, 0);\n' % \
1465 (self.base_name, base, self.size-1)
1466
1467 def makeWrite(self):
1468 if (self.ctype == 'float' or self.ctype == 'double'):
1469 error(0, 'Attempt to write control register as FP')
1470 if self.write_code != None:
1471 return self.buildWriteCode('setMiscReg')
1472 wb = 'xc->setMiscReg(%s, %s);\n' % \
1473 (self.reg_spec, self.base_name)
1474 wb += 'if (traceData) { traceData->setData(%s); }' % \
1475 self.base_name
1476 return wb
1477
1478class ControlBitfieldOperand(ControlRegOperand):
1479 def makeRead(self):
1480 bit_select = 0
1481 if (self.ctype == 'float' or self.ctype == 'double'):
1482 error(0, 'Attempt to read control register as FP')
1483 if self.read_code != None:
1484 return self.buildReadCode('readMiscReg')
1485 base = 'xc->readMiscReg(%s)' % self.reg_spec

--- 613 unchanged lines hidden --- 		1434class ControlBitfieldOperand(ControlRegOperand):
1435 def makeRead(self):
1436 bit_select = 0
1437 if (self.ctype == 'float' or self.ctype == 'double'):
1438 error(0, 'Attempt to read control register as FP')
1439 if self.read_code != None:
1440 return self.buildReadCode('readMiscReg')
1441 base = 'xc->readMiscReg(%s)' % self.reg_spec

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