isa_parser.py (6311:30d1e27daf68) isa_parser.py (6314:781969fbeca9)
1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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1168#
1169# Base class for operand descriptors. An instance of this class (or
1170# actually a class derived from this one) represents a specific
1171# operand for a code block (e.g, "Rc.sq" as a dest). Intermediate
1172# derived classes encapsulates the traits of a particular operand type
1173# (e.g., "32-bit integer register").
1174#
1175class Operand(object):
1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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1168#
1169# Base class for operand descriptors. An instance of this class (or
1170# actually a class derived from this one) represents a specific
1171# operand for a code block (e.g, "Rc.sq" as a dest). Intermediate
1172# derived classes encapsulates the traits of a particular operand type
1173# (e.g., "32-bit integer register").
1174#
1175class Operand(object):
1176 def buildReadCode(self, func = None, width = None):
1176 def buildReadCode(self, func = None):
1177 code = self.read_code % {"name": self.base_name,
1178 "func": func,
1177 code = self.read_code % {"name": self.base_name,
1178 "func": func,
1179 "width": width,
1180 "op_idx": self.src_reg_idx,
1181 "reg_idx": self.reg_spec,
1182 "size": self.size,
1183 "ctype": self.ctype}
1184 if self.size != self.dflt_size:
1185 return '%s = bits(%s, %d, 0);\n' % \
1186 (self.base_name, code, self.size-1)
1187 else:
1188 return '%s = %s;\n' % \
1189 (self.base_name, code)
1190
1179 "op_idx": self.src_reg_idx,
1180 "reg_idx": self.reg_spec,
1181 "size": self.size,
1182 "ctype": self.ctype}
1183 if self.size != self.dflt_size:
1184 return '%s = bits(%s, %d, 0);\n' % \
1185 (self.base_name, code, self.size-1)
1186 else:
1187 return '%s = %s;\n' % \
1188 (self.base_name, code)
1189
1191 def buildWriteCode(self, func = None, width = None):
1190 def buildWriteCode(self, func = None):
1192 if (self.size != self.dflt_size and self.is_signed):
1193 final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
1194 else:
1195 final_val = self.base_name
1196 code = self.write_code % {"name": self.base_name,
1197 "func": func,
1191 if (self.size != self.dflt_size and self.is_signed):
1192 final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
1193 else:
1194 final_val = self.base_name
1195 code = self.write_code % {"name": self.base_name,
1196 "func": func,
1198 "width": width,
1199 "op_idx": self.dest_reg_idx,
1200 "reg_idx": self.reg_spec,
1201 "size": self.size,
1202 "ctype": self.ctype,
1203 "final_val": final_val}
1204 return '''
1205 {
1206 %s final_val = %s;

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1353 (self.src_reg_idx, self.reg_spec)
1354 if self.is_dest:
1355 c += '\n\t_destRegIdx[%d] = %s + FP_Base_DepTag;' % \
1356 (self.dest_reg_idx, self.reg_spec)
1357 return c
1358
1359 def makeRead(self):
1360 bit_select = 0
1197 "op_idx": self.dest_reg_idx,
1198 "reg_idx": self.reg_spec,
1199 "size": self.size,
1200 "ctype": self.ctype,
1201 "final_val": final_val}
1202 return '''
1203 {
1204 %s final_val = %s;

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1351 (self.src_reg_idx, self.reg_spec)
1352 if self.is_dest:
1353 c += '\n\t_destRegIdx[%d] = %s + FP_Base_DepTag;' % \
1354 (self.dest_reg_idx, self.reg_spec)
1355 return c
1356
1357 def makeRead(self):
1358 bit_select = 0
1361 width = 0;
1362 if (self.ctype == 'float'):
1359 if (self.ctype == 'float' or self.ctype == 'double'):
1363 func = 'readFloatRegOperand'
1360 func = 'readFloatRegOperand'
1364 width = 32;
1365 elif (self.ctype == 'double'):
1366 func = 'readFloatRegOperand'
1367 width = 64;
1368 else:
1369 func = 'readFloatRegOperandBits'
1361 else:
1362 func = 'readFloatRegOperandBits'
1370 if (self.ctype == 'uint32_t'):
1371 width = 32;
1372 elif (self.ctype == 'uint64_t'):
1373 width = 64;
1374 if (self.size != self.dflt_size):
1375 bit_select = 1
1363 if (self.size != self.dflt_size):
1364 bit_select = 1
1376 if width:
1377 base = 'xc->%s(this, %d, %d)' % \
1378 (func, self.src_reg_idx, width)
1379 else:
1380 base = 'xc->%s(this, %d)' % \
1381 (func, self.src_reg_idx)
1365 base = 'xc->%s(this, %d)' % (func, self.src_reg_idx)
1382 if self.read_code != None:
1366 if self.read_code != None:
1383 return self.buildReadCode(func, width)
1367 return self.buildReadCode(func)
1384 if bit_select:
1385 return '%s = bits(%s, %d, 0);\n' % \
1386 (self.base_name, base, self.size-1)
1387 else:
1388 return '%s = %s;\n' % (self.base_name, base)
1389
1390 def makeWrite(self):
1391 final_val = self.base_name
1392 final_ctype = self.ctype
1368 if bit_select:
1369 return '%s = bits(%s, %d, 0);\n' % \
1370 (self.base_name, base, self.size-1)
1371 else:
1372 return '%s = %s;\n' % (self.base_name, base)
1373
1374 def makeWrite(self):
1375 final_val = self.base_name
1376 final_ctype = self.ctype
1393 widthSpecifier = ''
1394 width = 0
1395 if (self.ctype == 'float'):
1396 width = 32
1377 if (self.ctype == 'float' or self.ctype == 'double'):
1397 func = 'setFloatRegOperand'
1378 func = 'setFloatRegOperand'
1398 elif (self.ctype == 'double'):
1399 width = 64
1400 func = 'setFloatRegOperand'
1401 elif (self.ctype == 'uint32_t'):
1379 elif (self.ctype == 'uint32_t' or self.ctype == 'uint64_t'):
1402 func = 'setFloatRegOperandBits'
1380 func = 'setFloatRegOperandBits'
1403 width = 32
1404 elif (self.ctype == 'uint64_t'):
1405 func = 'setFloatRegOperandBits'
1406 width = 64
1407 else:
1408 func = 'setFloatRegOperandBits'
1409 final_ctype = 'uint%d_t' % self.dflt_size
1410 if (self.size != self.dflt_size and self.is_signed):
1411 final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
1412 if self.write_code != None:
1381 else:
1382 func = 'setFloatRegOperandBits'
1383 final_ctype = 'uint%d_t' % self.dflt_size
1384 if (self.size != self.dflt_size and self.is_signed):
1385 final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
1386 if self.write_code != None:
1413 return self.buildWriteCode(func, width)
1414 if width:
1415 widthSpecifier = ', %d' % width
1387 return self.buildWriteCode(func)
1416 wb = '''
1417 {
1418 %s final_val = %s;
1388 wb = '''
1389 {
1390 %s final_val = %s;
1419 xc->%s(this, %d, final_val%s);\n
1391 xc->%s(this, %d, final_val);\n
1420 if (traceData) { traceData->setData(final_val); }
1392 if (traceData) { traceData->setData(final_val); }
1421 }''' % (final_ctype, final_val, func, self.dest_reg_idx,
1422 widthSpecifier)
1393 }''' % (final_ctype, final_val, func, self.dest_reg_idx)
1423 return wb
1424
1425class ControlRegOperand(Operand):
1426 def isReg(self):
1427 return 1
1428
1429 def isControlReg(self):
1430 return 1

--- 697 unchanged lines hidden --- 		1394 return wb
1395
1396class ControlRegOperand(Operand):
1397 def isReg(self):
1398 return 1
1399
1400 def isControlReg(self):
1401 return 1

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