isa_parser.py (6178:2bbb49ca07a8) isa_parser.py (6311:30d1e27daf68)
1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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339# Define the mapping from operand names to operand classes and other
340# traits. Stored in operandNameMap.
341def p_def_operands(t):
342 'def_operands : DEF OPERANDS CODELIT SEMI'
343 if not globals().has_key('operandTypeMap'):
344 error(t.lexer.lineno,
345 'error: operand types must be defined before operands')
346 try:
1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 330 unchanged lines hidden (view full) ---

339# Define the mapping from operand names to operand classes and other
340# traits. Stored in operandNameMap.
341def p_def_operands(t):
342 'def_operands : DEF OPERANDS CODELIT SEMI'
343 if not globals().has_key('operandTypeMap'):
344 error(t.lexer.lineno,
345 'error: operand types must be defined before operands')
346 try:
347 userDict = eval('{' + t[3] + '}')
347 userDict = eval('{' + t[3] + '}', exportContext)
348 except Exception, exc:
349 error(t.lexer.lineno,
350 'error: %s in def operands block "%s".' % (exc, t[3]))
351 buildOperandNameMap(userDict, t.lexer.lineno)
352 t[0] = GenCode() # contributes nothing to the output C++ file
353
354# A bitfield definition looks like:
355# 'def [signed] bitfield <ID> [<first>:<last>]'

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1168#
1169# Base class for operand descriptors. An instance of this class (or
1170# actually a class derived from this one) represents a specific
1171# operand for a code block (e.g, "Rc.sq" as a dest). Intermediate
1172# derived classes encapsulates the traits of a particular operand type
1173# (e.g., "32-bit integer register").
1174#
1175class Operand(object):
348 except Exception, exc:
349 error(t.lexer.lineno,
350 'error: %s in def operands block "%s".' % (exc, t[3]))
351 buildOperandNameMap(userDict, t.lexer.lineno)
352 t[0] = GenCode() # contributes nothing to the output C++ file
353
354# A bitfield definition looks like:
355# 'def [signed] bitfield <ID> [<first>:<last>]'

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1168#
1169# Base class for operand descriptors. An instance of this class (or
1170# actually a class derived from this one) represents a specific
1171# operand for a code block (e.g, "Rc.sq" as a dest). Intermediate
1172# derived classes encapsulates the traits of a particular operand type
1173# (e.g., "32-bit integer register").
1174#
1175class Operand(object):
1176 def buildReadCode(self, func = None, width = None):
1177 code = self.read_code % {"name": self.base_name,
1178 "func": func,
1179 "width": width,
1180 "op_idx": self.src_reg_idx,
1181 "reg_idx": self.reg_spec,
1182 "size": self.size,
1183 "ctype": self.ctype}
1184 if self.size != self.dflt_size:
1185 return '%s = bits(%s, %d, 0);\n' % \
1186 (self.base_name, code, self.size-1)
1187 else:
1188 return '%s = %s;\n' % \
1189 (self.base_name, code)
1190
1191 def buildWriteCode(self, func = None, width = None):
1192 if (self.size != self.dflt_size and self.is_signed):
1193 final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
1194 else:
1195 final_val = self.base_name
1196 code = self.write_code % {"name": self.base_name,
1197 "func": func,
1198 "width": width,
1199 "op_idx": self.dest_reg_idx,
1200 "reg_idx": self.reg_spec,
1201 "size": self.size,
1202 "ctype": self.ctype,
1203 "final_val": final_val}
1204 return '''
1205 {
1206 %s final_val = %s;
1207 %s;
1208 if (traceData) { traceData->setData(final_val); }
1209 }''' % (self.dflt_ctype, final_val, code)
1210
1176 def __init__(self, full_name, ext, is_src, is_dest):
1177 self.full_name = full_name
1178 self.ext = ext
1179 self.is_src = is_src
1180 self.is_dest = is_dest
1181 # The 'effective extension' (eff_ext) is either the actual
1182 # extension, if one was explicitly provided, or the default.
1183 if ext:

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1267 if self.is_dest:
1268 c += '\n\t_destRegIdx[%d] = %s;' % \
1269 (self.dest_reg_idx, self.reg_spec)
1270 return c
1271
1272 def makeRead(self):
1273 if (self.ctype == 'float' or self.ctype == 'double'):
1274 error(0, 'Attempt to read integer register as FP')
1211 def __init__(self, full_name, ext, is_src, is_dest):
1212 self.full_name = full_name
1213 self.ext = ext
1214 self.is_src = is_src
1215 self.is_dest = is_dest
1216 # The 'effective extension' (eff_ext) is either the actual
1217 # extension, if one was explicitly provided, or the default.
1218 if ext:

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1302 if self.is_dest:
1303 c += '\n\t_destRegIdx[%d] = %s;' % \
1304 (self.dest_reg_idx, self.reg_spec)
1305 return c
1306
1307 def makeRead(self):
1308 if (self.ctype == 'float' or self.ctype == 'double'):
1309 error(0, 'Attempt to read integer register as FP')
1310 if self.read_code != None:
1311 return self.buildReadCode('readIntRegOperand')
1275 if (self.size == self.dflt_size):
1276 return '%s = xc->readIntRegOperand(this, %d);\n' % \
1277 (self.base_name, self.src_reg_idx)
1278 elif (self.size > self.dflt_size):
1279 int_reg_val = 'xc->readIntRegOperand(this, %d)' % \
1280 (self.src_reg_idx)
1281 if (self.is_signed):
1282 int_reg_val = 'sext<%d>(%s)' % (self.dflt_size, int_reg_val)
1283 return '%s = %s;\n' % (self.base_name, int_reg_val)
1284 else:
1285 return '%s = bits(xc->readIntRegOperand(this, %d), %d, 0);\n' % \
1286 (self.base_name, self.src_reg_idx, self.size-1)
1287
1288 def makeWrite(self):
1289 if (self.ctype == 'float' or self.ctype == 'double'):
1290 error(0, 'Attempt to write integer register as FP')
1312 if (self.size == self.dflt_size):
1313 return '%s = xc->readIntRegOperand(this, %d);\n' % \
1314 (self.base_name, self.src_reg_idx)
1315 elif (self.size > self.dflt_size):
1316 int_reg_val = 'xc->readIntRegOperand(this, %d)' % \
1317 (self.src_reg_idx)
1318 if (self.is_signed):
1319 int_reg_val = 'sext<%d>(%s)' % (self.dflt_size, int_reg_val)
1320 return '%s = %s;\n' % (self.base_name, int_reg_val)
1321 else:
1322 return '%s = bits(xc->readIntRegOperand(this, %d), %d, 0);\n' % \
1323 (self.base_name, self.src_reg_idx, self.size-1)
1324
1325 def makeWrite(self):
1326 if (self.ctype == 'float' or self.ctype == 'double'):
1327 error(0, 'Attempt to write integer register as FP')
1328 if self.write_code != None:
1329 return self.buildWriteCode('setIntRegOperand')
1291 if (self.size != self.dflt_size and self.is_signed):
1292 final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
1293 else:
1294 final_val = self.base_name
1295 wb = '''
1296 {
1297 %s final_val = %s;
1298 xc->setIntRegOperand(this, %d, final_val);\n

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1335 if (self.size != self.dflt_size):
1336 bit_select = 1
1337 if width:
1338 base = 'xc->%s(this, %d, %d)' % \
1339 (func, self.src_reg_idx, width)
1340 else:
1341 base = 'xc->%s(this, %d)' % \
1342 (func, self.src_reg_idx)
1330 if (self.size != self.dflt_size and self.is_signed):
1331 final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
1332 else:
1333 final_val = self.base_name
1334 wb = '''
1335 {
1336 %s final_val = %s;
1337 xc->setIntRegOperand(this, %d, final_val);\n

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1374 if (self.size != self.dflt_size):
1375 bit_select = 1
1376 if width:
1377 base = 'xc->%s(this, %d, %d)' % \
1378 (func, self.src_reg_idx, width)
1379 else:
1380 base = 'xc->%s(this, %d)' % \
1381 (func, self.src_reg_idx)
1382 if self.read_code != None:
1383 return self.buildReadCode(func, width)
1343 if bit_select:
1344 return '%s = bits(%s, %d, 0);\n' % \
1345 (self.base_name, base, self.size-1)
1346 else:
1347 return '%s = %s;\n' % (self.base_name, base)
1348
1349 def makeWrite(self):
1350 final_val = self.base_name

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1363 elif (self.ctype == 'uint64_t'):
1364 func = 'setFloatRegOperandBits'
1365 width = 64
1366 else:
1367 func = 'setFloatRegOperandBits'
1368 final_ctype = 'uint%d_t' % self.dflt_size
1369 if (self.size != self.dflt_size and self.is_signed):
1370 final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
1384 if bit_select:
1385 return '%s = bits(%s, %d, 0);\n' % \
1386 (self.base_name, base, self.size-1)
1387 else:
1388 return '%s = %s;\n' % (self.base_name, base)
1389
1390 def makeWrite(self):
1391 final_val = self.base_name

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1404 elif (self.ctype == 'uint64_t'):
1405 func = 'setFloatRegOperandBits'
1406 width = 64
1407 else:
1408 func = 'setFloatRegOperandBits'
1409 final_ctype = 'uint%d_t' % self.dflt_size
1410 if (self.size != self.dflt_size and self.is_signed):
1411 final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
1412 if self.write_code != None:
1413 return self.buildWriteCode(func, width)
1371 if width:
1372 widthSpecifier = ', %d' % width
1373 wb = '''
1374 {
1375 %s final_val = %s;
1376 xc->%s(this, %d, final_val%s);\n
1377 if (traceData) { traceData->setData(final_val); }
1378 }''' % (final_ctype, final_val, func, self.dest_reg_idx,

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1395 c += '\n\t_destRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
1396 (self.dest_reg_idx, self.reg_spec)
1397 return c
1398
1399 def makeRead(self):
1400 bit_select = 0
1401 if (self.ctype == 'float' or self.ctype == 'double'):
1402 error(0, 'Attempt to read control register as FP')
1414 if width:
1415 widthSpecifier = ', %d' % width
1416 wb = '''
1417 {
1418 %s final_val = %s;
1419 xc->%s(this, %d, final_val%s);\n
1420 if (traceData) { traceData->setData(final_val); }
1421 }''' % (final_ctype, final_val, func, self.dest_reg_idx,

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1438 c += '\n\t_destRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
1439 (self.dest_reg_idx, self.reg_spec)
1440 return c
1441
1442 def makeRead(self):
1443 bit_select = 0
1444 if (self.ctype == 'float' or self.ctype == 'double'):
1445 error(0, 'Attempt to read control register as FP')
1446 if self.read_code != None:
1447 return self.buildReadCode('readMiscRegOperand')
1403 base = 'xc->readMiscRegOperand(this, %s)' % self.src_reg_idx
1404 if self.size == self.dflt_size:
1405 return '%s = %s;\n' % (self.base_name, base)
1406 else:
1407 return '%s = bits(%s, %d, 0);\n' % \
1408 (self.base_name, base, self.size-1)
1409
1410 def makeWrite(self):
1411 if (self.ctype == 'float' or self.ctype == 'double'):
1412 error(0, 'Attempt to write control register as FP')
1448 base = 'xc->readMiscRegOperand(this, %s)' % self.src_reg_idx
1449 if self.size == self.dflt_size:
1450 return '%s = %s;\n' % (self.base_name, base)
1451 else:
1452 return '%s = bits(%s, %d, 0);\n' % \
1453 (self.base_name, base, self.size-1)
1454
1455 def makeWrite(self):
1456 if (self.ctype == 'float' or self.ctype == 'double'):
1457 error(0, 'Attempt to write control register as FP')
1458 if self.write_code != None:
1459 return self.buildWriteCode('setMiscRegOperand')
1413 wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
1414 (self.dest_reg_idx, self.base_name)
1415 wb += 'if (traceData) { traceData->setData(%s); }' % \
1416 self.base_name
1417 return wb
1418
1419class IControlRegOperand(Operand):
1420 def isReg(self):

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1432 c += '\n\t_destRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
1433 (self.dest_reg_idx, self.reg_spec)
1434 return c
1435
1436 def makeRead(self):
1437 bit_select = 0
1438 if (self.ctype == 'float' or self.ctype == 'double'):
1439 error(0, 'Attempt to read control register as FP')
1460 wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
1461 (self.dest_reg_idx, self.base_name)
1462 wb += 'if (traceData) { traceData->setData(%s); }' % \
1463 self.base_name
1464 return wb
1465
1466class IControlRegOperand(Operand):
1467 def isReg(self):

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1479 c += '\n\t_destRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
1480 (self.dest_reg_idx, self.reg_spec)
1481 return c
1482
1483 def makeRead(self):
1484 bit_select = 0
1485 if (self.ctype == 'float' or self.ctype == 'double'):
1486 error(0, 'Attempt to read control register as FP')
1487 if self.read_code != None:
1488 return self.buildReadCode('readMiscReg')
1440 base = 'xc->readMiscReg(%s)' % self.reg_spec
1441 if self.size == self.dflt_size:
1442 return '%s = %s;\n' % (self.base_name, base)
1443 else:
1444 return '%s = bits(%s, %d, 0);\n' % \
1445 (self.base_name, base, self.size-1)
1446
1447 def makeWrite(self):
1448 if (self.ctype == 'float' or self.ctype == 'double'):
1449 error(0, 'Attempt to write control register as FP')
1489 base = 'xc->readMiscReg(%s)' % self.reg_spec
1490 if self.size == self.dflt_size:
1491 return '%s = %s;\n' % (self.base_name, base)
1492 else:
1493 return '%s = bits(%s, %d, 0);\n' % \
1494 (self.base_name, base, self.size-1)
1495
1496 def makeWrite(self):
1497 if (self.ctype == 'float' or self.ctype == 'double'):
1498 error(0, 'Attempt to write control register as FP')
1499 if self.write_code != None:
1500 return self.buildWriteCode('setMiscReg')
1450 wb = 'xc->setMiscReg(%s, %s);\n' % \
1451 (self.reg_spec, self.base_name)
1452 wb += 'if (traceData) { traceData->setData(%s); }' % \
1453 self.base_name
1454 return wb
1455
1456class ControlBitfieldOperand(ControlRegOperand):
1457 def makeRead(self):
1458 bit_select = 0
1459 if (self.ctype == 'float' or self.ctype == 'double'):
1460 error(0, 'Attempt to read control register as FP')
1501 wb = 'xc->setMiscReg(%s, %s);\n' % \
1502 (self.reg_spec, self.base_name)
1503 wb += 'if (traceData) { traceData->setData(%s); }' % \
1504 self.base_name
1505 return wb
1506
1507class ControlBitfieldOperand(ControlRegOperand):
1508 def makeRead(self):
1509 bit_select = 0
1510 if (self.ctype == 'float' or self.ctype == 'double'):
1511 error(0, 'Attempt to read control register as FP')
1512 if self.read_code != None:
1513 return self.buildReadCode('readMiscReg')
1461 base = 'xc->readMiscReg(%s)' % self.reg_spec
1462 name = self.base_name
1463 return '%s = bits(%s, %s_HI, %s_LO);' % \
1464 (name, base, name, name)
1465
1466 def makeWrite(self):
1467 if (self.ctype == 'float' or self.ctype == 'double'):
1468 error(0, 'Attempt to write control register as FP')
1514 base = 'xc->readMiscReg(%s)' % self.reg_spec
1515 name = self.base_name
1516 return '%s = bits(%s, %s_HI, %s_LO);' % \
1517 (name, base, name, name)
1518
1519 def makeWrite(self):
1520 if (self.ctype == 'float' or self.ctype == 'double'):
1521 error(0, 'Attempt to write control register as FP')
1522 if self.write_code != None:
1523 return self.buildWriteCode('setMiscReg')
1469 base = 'xc->readMiscReg(%s)' % self.reg_spec
1470 name = self.base_name
1471 wb_val = 'insertBits(%s, %s_HI, %s_LO, %s)' % \
1472 (base, name, name, self.base_name)
1473 wb = 'xc->setMiscRegOperand(this, %s, %s );\n' % (self.dest_reg_idx, wb_val)
1474 wb += 'if (traceData) { traceData->setData(%s); }' % \
1475 self.base_name
1476 return wb

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1488 # Declare memory data variable.
1489 if self.ctype in ['Twin32_t','Twin64_t']:
1490 return "%s %s; %s.a = 0; %s.b = 0;\n" % (self.ctype, self.base_name,
1491 self.base_name, self.base_name)
1492 c = '%s %s = 0;\n' % (self.ctype, self.base_name)
1493 return c
1494
1495 def makeRead(self):
1524 base = 'xc->readMiscReg(%s)' % self.reg_spec
1525 name = self.base_name
1526 wb_val = 'insertBits(%s, %s_HI, %s_LO, %s)' % \
1527 (base, name, name, self.base_name)
1528 wb = 'xc->setMiscRegOperand(this, %s, %s );\n' % (self.dest_reg_idx, wb_val)
1529 wb += 'if (traceData) { traceData->setData(%s); }' % \
1530 self.base_name
1531 return wb

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1543 # Declare memory data variable.
1544 if self.ctype in ['Twin32_t','Twin64_t']:
1545 return "%s %s; %s.a = 0; %s.b = 0;\n" % (self.ctype, self.base_name,
1546 self.base_name, self.base_name)
1547 c = '%s %s = 0;\n' % (self.ctype, self.base_name)
1548 return c
1549
1550 def makeRead(self):
1551 if self.read_code != None:
1552 return self.buildReadCode()
1496 return ''
1497
1498 def makeWrite(self):
1553 return ''
1554
1555 def makeWrite(self):
1556 if self.write_code != None:
1557 return self.buildWriteCode()
1499 return ''
1500
1501 # Return the memory access size *in bits*, suitable for
1502 # forming a type via "uint%d_t". Divide by 8 if you want bytes.
1503 def makeAccSize(self):
1504 return self.size
1505
1506class UPCOperand(Operand):
1507 def makeConstructor(self):
1508 return ''
1509
1510 def makeRead(self):
1558 return ''
1559
1560 # Return the memory access size *in bits*, suitable for
1561 # forming a type via "uint%d_t". Divide by 8 if you want bytes.
1562 def makeAccSize(self):
1563 return self.size
1564
1565class UPCOperand(Operand):
1566 def makeConstructor(self):
1567 return ''
1568
1569 def makeRead(self):
1570 if self.read_code != None:
1571 return self.buildReadCode('readMicroPC')
1511 return '%s = xc->readMicroPC();\n' % self.base_name
1512
1513 def makeWrite(self):
1572 return '%s = xc->readMicroPC();\n' % self.base_name
1573
1574 def makeWrite(self):
1575 if self.write_code != None:
1576 return self.buildWriteCode('setMicroPC')
1514 return 'xc->setMicroPC(%s);\n' % self.base_name
1515
1516class NUPCOperand(Operand):
1517 def makeConstructor(self):
1518 return ''
1519
1520 def makeRead(self):
1577 return 'xc->setMicroPC(%s);\n' % self.base_name
1578
1579class NUPCOperand(Operand):
1580 def makeConstructor(self):
1581 return ''
1582
1583 def makeRead(self):
1584 if self.read_code != None:
1585 return self.buildReadCode('readNextMicroPC')
1521 return '%s = xc->readNextMicroPC();\n' % self.base_name
1522
1523 def makeWrite(self):
1586 return '%s = xc->readNextMicroPC();\n' % self.base_name
1587
1588 def makeWrite(self):
1589 if self.write_code != None:
1590 return self.buildWriteCode('setNextMicroPC')
1524 return 'xc->setNextMicroPC(%s);\n' % self.base_name
1525
1526class NPCOperand(Operand):
1527 def makeConstructor(self):
1528 return ''
1529
1530 def makeRead(self):
1591 return 'xc->setNextMicroPC(%s);\n' % self.base_name
1592
1593class NPCOperand(Operand):
1594 def makeConstructor(self):
1595 return ''
1596
1597 def makeRead(self):
1598 if self.read_code != None:
1599 return self.buildReadCode('readNextPC')
1531 return '%s = xc->readNextPC();\n' % self.base_name
1532
1533 def makeWrite(self):
1600 return '%s = xc->readNextPC();\n' % self.base_name
1601
1602 def makeWrite(self):
1603 if self.write_code != None:
1604 return self.buildWriteCode('setNextPC')
1534 return 'xc->setNextPC(%s);\n' % self.base_name
1535
1536class NNPCOperand(Operand):
1537 def makeConstructor(self):
1538 return ''
1539
1540 def makeRead(self):
1605 return 'xc->setNextPC(%s);\n' % self.base_name
1606
1607class NNPCOperand(Operand):
1608 def makeConstructor(self):
1609 return ''
1610
1611 def makeRead(self):
1612 if self.read_code != None:
1613 return self.buildReadCode('readNextNPC')
1541 return '%s = xc->readNextNPC();\n' % self.base_name
1542
1543 def makeWrite(self):
1614 return '%s = xc->readNextNPC();\n' % self.base_name
1615
1616 def makeWrite(self):
1617 if self.write_code != None:
1618 return self.buildWriteCode('setNextNPC')
1544 return 'xc->setNextNPC(%s);\n' % self.base_name
1545
1546def buildOperandNameMap(userDict, lineno):
1547 global operandNameMap
1548 operandNameMap = {}
1549 for (op_name, val) in userDict.iteritems():
1619 return 'xc->setNextNPC(%s);\n' % self.base_name
1620
1621def buildOperandNameMap(userDict, lineno):
1622 global operandNameMap
1623 operandNameMap = {}
1624 for (op_name, val) in userDict.iteritems():
1550 (base_cls_name, dflt_ext, reg_spec, flags, sort_pri) = val
1625 (base_cls_name, dflt_ext, reg_spec, flags, sort_pri) = val[:5]
1626 if len(val) > 5:
1627 read_code = val[5]
1628 else:
1629 read_code = None
1630 if len(val) > 6:
1631 write_code = val[6]
1632 else:
1633 write_code = None
1634 if len(val) > 7:
1635 error(lineno,
1636 'error: too many attributes for operand "%s"' %
1637 base_cls_name)
1638
1551 (dflt_size, dflt_ctype, dflt_is_signed) = operandTypeMap[dflt_ext]
1552 # Canonical flag structure is a triple of lists, where each list
1553 # indicates the set of flags implied by this operand always, when
1554 # used as a source, and when used as a dest, respectively.
1555 # For simplicity this can be initialized using a variety of fairly
1556 # obvious shortcuts; we convert these to canonical form here.
1557 if not flags:
1558 # no flags specified (e.g., 'None')

--- 8 unchanged lines hidden (view full) ---

1567 # it's a tuple: it should be a triple,
1568 # but each item could be a single string or a list
1569 (uncond_flags, src_flags, dest_flags) = flags
1570 flags = (makeList(uncond_flags),
1571 makeList(src_flags), makeList(dest_flags))
1572 # Accumulate attributes of new operand class in tmp_dict
1573 tmp_dict = {}
1574 for attr in ('dflt_ext', 'reg_spec', 'flags', 'sort_pri',
1639 (dflt_size, dflt_ctype, dflt_is_signed) = operandTypeMap[dflt_ext]
1640 # Canonical flag structure is a triple of lists, where each list
1641 # indicates the set of flags implied by this operand always, when
1642 # used as a source, and when used as a dest, respectively.
1643 # For simplicity this can be initialized using a variety of fairly
1644 # obvious shortcuts; we convert these to canonical form here.
1645 if not flags:
1646 # no flags specified (e.g., 'None')

--- 8 unchanged lines hidden (view full) ---

1655 # it's a tuple: it should be a triple,
1656 # but each item could be a single string or a list
1657 (uncond_flags, src_flags, dest_flags) = flags
1658 flags = (makeList(uncond_flags),
1659 makeList(src_flags), makeList(dest_flags))
1660 # Accumulate attributes of new operand class in tmp_dict
1661 tmp_dict = {}
1662 for attr in ('dflt_ext', 'reg_spec', 'flags', 'sort_pri',
1575 'dflt_size', 'dflt_ctype', 'dflt_is_signed'):
1663 'dflt_size', 'dflt_ctype', 'dflt_is_signed',
1664 'read_code', 'write_code'):
1576 tmp_dict[attr] = eval(attr)
1577 tmp_dict['base_name'] = op_name
1578 # New class name will be e.g. "IntReg_Ra"
1579 cls_name = base_cls_name + '_' + op_name
1580 # Evaluate string arg to get class object. Note that the
1581 # actual base class for "IntReg" is "IntRegOperand", i.e. we
1582 # have to append "Operand".
1583 try:

--- 455 unchanged lines hidden --- 		1665 tmp_dict[attr] = eval(attr)
1666 tmp_dict['base_name'] = op_name
1667 # New class name will be e.g. "IntReg_Ra"
1668 cls_name = base_cls_name + '_' + op_name
1669 # Evaluate string arg to get class object. Note that the
1670 # actual base class for "IntReg" is "IntRegOperand", i.e. we
1671 # have to append "Operand".
1672 try:

--- 455 unchanged lines hidden ---