isa_parser.py (5222:bb733a878f85) isa_parser.py (5228:b08c9c42907a)
1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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1409 if (self.ctype == 'float' or self.ctype == 'double'):
1410 error(0, 'Attempt to write control register as FP')
1411 wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
1412 (self.dest_reg_idx, self.base_name)
1413 wb += 'if (traceData) { traceData->setData(%s); }' % \
1414 self.base_name
1415 return wb
1416
1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 1400 unchanged lines hidden (view full) ---

1409 if (self.ctype == 'float' or self.ctype == 'double'):
1410 error(0, 'Attempt to write control register as FP')
1411 wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
1412 (self.dest_reg_idx, self.base_name)
1413 wb += 'if (traceData) { traceData->setData(%s); }' % \
1414 self.base_name
1415 return wb
1416
1417class IControlRegOperand(Operand):
1418 def isReg(self):
1419 return 1
1420
1421 def isIControlReg(self):
1422 return 1
1423
1424 def makeConstructor(self):
1425 c = ''
1426 if self.is_src:
1427 c += '\n\t_srcRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
1428 (self.src_reg_idx, self.reg_spec)
1429 if self.is_dest:
1430 c += '\n\t_destRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
1431 (self.dest_reg_idx, self.reg_spec)
1432 return c
1433
1434 def makeRead(self):
1435 bit_select = 0
1436 if (self.ctype == 'float' or self.ctype == 'double'):
1437 error(0, 'Attempt to read control register as FP')
1438 base = 'xc->readMiscReg(%s)' % self.reg_spec
1439 if self.size == self.dflt_size:
1440 return '%s = %s;\n' % (self.base_name, base)
1441 else:
1442 return '%s = bits(%s, %d, 0);\n' % \
1443 (self.base_name, base, self.size-1)
1444
1445 def makeWrite(self):
1446 if (self.ctype == 'float' or self.ctype == 'double'):
1447 error(0, 'Attempt to write control register as FP')
1448 wb = 'xc->setMiscReg(%s, %s);\n' % \
1449 (self.reg_spec, self.base_name)
1450 wb += 'if (traceData) { traceData->setData(%s); }' % \
1451 self.base_name
1452 return wb
1453
1454class ControlBitfieldOperand(ControlRegOperand):
1455 def makeRead(self):
1456 bit_select = 0
1457 if (self.ctype == 'float' or self.ctype == 'double'):
1458 error(0, 'Attempt to read control register as FP')
1459 base = 'xc->readMiscReg(%s)' % self.reg_spec
1460 name = self.base_name
1461 return '%s = bits(%s, %s_HI, %s_LO);' % \

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1605 # groups are returned (base and ext, not full name as above).
1606 # Used for subtituting '_' for '.' to make C++ identifiers.
1607 operandsWithExtREString = (r'(?<![\w\.])(%s)\.(\w+)(?![\w\.])'
1608 % string.join(operands, '|'))
1609
1610 global operandsWithExtRE
1611 operandsWithExtRE = re.compile(operandsWithExtREString, re.MULTILINE)
1612
1417class ControlBitfieldOperand(ControlRegOperand):
1418 def makeRead(self):
1419 bit_select = 0
1420 if (self.ctype == 'float' or self.ctype == 'double'):
1421 error(0, 'Attempt to read control register as FP')
1422 base = 'xc->readMiscReg(%s)' % self.reg_spec
1423 name = self.base_name
1424 return '%s = bits(%s, %s_HI, %s_LO);' % \

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1568 # groups are returned (base and ext, not full name as above).
1569 # Used for subtituting '_' for '.' to make C++ identifiers.
1570 operandsWithExtREString = (r'(?<![\w\.])(%s)\.(\w+)(?![\w\.])'
1571 % string.join(operands, '|'))
1572
1573 global operandsWithExtRE
1574 operandsWithExtRE = re.compile(operandsWithExtREString, re.MULTILINE)
1575
1576maxInstSrcRegs = 0
1577maxInstDestRegs = 0
1613
1614class OperandList:
1615
1616 # Find all the operands in the given code block. Returns an operand
1617 # descriptor list (instance of class OperandList).
1618 def __init__(self, code):
1619 self.items = []
1620 self.bases = {}

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1668 if op_desc.isFloatReg():
1669 self.numFPDestRegs += 1
1670 elif op_desc.isIntReg():
1671 self.numIntDestRegs += 1
1672 elif op_desc.isMem():
1673 if self.memOperand:
1674 error(0, "Code block has more than one memory operand.")
1675 self.memOperand = op_desc
1578
1579class OperandList:
1580
1581 # Find all the operands in the given code block. Returns an operand
1582 # descriptor list (instance of class OperandList).
1583 def __init__(self, code):
1584 self.items = []
1585 self.bases = {}

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1633 if op_desc.isFloatReg():
1634 self.numFPDestRegs += 1
1635 elif op_desc.isIntReg():
1636 self.numIntDestRegs += 1
1637 elif op_desc.isMem():
1638 if self.memOperand:
1639 error(0, "Code block has more than one memory operand.")
1640 self.memOperand = op_desc
1641 global maxInstSrcRegs
1642 global maxInstDestRegs
1643 if maxInstSrcRegs < self.numSrcRegs:
1644 maxInstSrcRegs = self.numSrcRegs
1645 if maxInstDestRegs < self.numDestRegs:
1646 maxInstDestRegs = self.numDestRegs
1676 # now make a final pass to finalize op_desc fields that may depend
1677 # on the register enumeration
1678 for op_desc in self.items:
1679 op_desc.finalize()
1680
1681 def __len__(self):
1682 return len(self.items)
1683

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1887
1888%(namespace_output)s
1889
1890} // namespace %(namespace)s
1891
1892%(decode_function)s
1893'''
1894
1647 # now make a final pass to finalize op_desc fields that may depend
1648 # on the register enumeration
1649 for op_desc in self.items:
1650 op_desc.finalize()
1651
1652 def __len__(self):
1653 return len(self.items)
1654

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1858
1859%(namespace_output)s
1860
1861} // namespace %(namespace)s
1862
1863%(decode_function)s
1864'''
1865
1866max_inst_regs_template = '''
1867/*
1868 * DO NOT EDIT THIS FILE!!!
1869 *
1870 * It was automatically generated from the ISA description in %(filename)s
1871 */
1895
1872
1873namespace %(namespace)s {
1874
1875 const int MaxInstSrcRegs = %(MaxInstSrcRegs)d;
1876 const int MaxInstDestRegs = %(MaxInstDestRegs)d;
1877
1878} // namespace %(namespace)s
1879
1880'''
1881
1882
1896# Update the output file only if the new contents are different from
1897# the current contents. Minimizes the files that need to be rebuilt
1898# after minor changes.
1899def update_if_needed(file, contents):
1900 update = False
1901 if os.access(file, os.R_OK):
1902 f = open(file, 'r')
1903 old_contents = f.read()

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1986 includes = '#include "decoder.hh"\n'
1987 includes += cpu.includes
1988 global_output = global_code.exec_output[cpu.name]
1989 namespace_output = namespace_code.exec_output[cpu.name]
1990 decode_function = ''
1991 update_if_needed(output_dir + '/' + cpu.filename,
1992 file_template % vars())
1993
1883# Update the output file only if the new contents are different from
1884# the current contents. Minimizes the files that need to be rebuilt
1885# after minor changes.
1886def update_if_needed(file, contents):
1887 update = False
1888 if os.access(file, os.R_OK):
1889 f = open(file, 'r')
1890 old_contents = f.read()

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1973 includes = '#include "decoder.hh"\n'
1974 includes += cpu.includes
1975 global_output = global_code.exec_output[cpu.name]
1976 namespace_output = namespace_code.exec_output[cpu.name]
1977 decode_function = ''
1978 update_if_needed(output_dir + '/' + cpu.filename,
1979 file_template % vars())
1980
1981 # The variable names here are hacky, but this will creat local variables
1982 # which will be referenced in vars() which have the value of the globals.
1983 global maxInstSrcRegs
1984 MaxInstSrcRegs = maxInstSrcRegs
1985 global maxInstDestRegs
1986 MaxInstDestRegs = maxInstDestRegs
1987 # max_inst_regs.hh
1988 update_if_needed(output_dir + '/max_inst_regs.hh', \
1989 max_inst_regs_template % vars())
1990
1994# global list of CpuModel objects (see cpu_models.py)
1995cpu_models = []
1996
1997# Called as script: get args from command line.
1998# Args are: <path to cpu_models.py> <isa desc file> <output dir> <cpu models>
1999if __name__ == '__main__':
2000 execfile(sys.argv[1]) # read in CpuModel definitions
2001 cpu_models = [CpuModel.dict[cpu] for cpu in sys.argv[4:]]
2002 parse_isa_desc(sys.argv[2], sys.argv[3])
1991# global list of CpuModel objects (see cpu_models.py)
1992cpu_models = []
1993
1994# Called as script: get args from command line.
1995# Args are: <path to cpu_models.py> <isa desc file> <output dir> <cpu models>
1996if __name__ == '__main__':
1997 execfile(sys.argv[1]) # read in CpuModel definitions
1998 cpu_models = [CpuModel.dict[cpu] for cpu in sys.argv[4:]]
1999 parse_isa_desc(sys.argv[2], sys.argv[3])