isa_parser.py (4662:96fb82f4f3d5) isa_parser.py (4663:449d172ca8ae)
1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28# Gabe Black
29# Korey Sewell
30
31import os
32import sys
33import re
34import string
35import traceback
36# get type names

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1406 return '%s = bits(%s, %d, 0);\n' % \
1407 (self.base_name, base, self.size-1)
1408
1409 def makeWrite(self):
1410 if (self.ctype == 'float' or self.ctype == 'double'):
1411 error(0, 'Attempt to write control register as FP')
1412 wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
1413 (self.dest_reg_idx, self.base_name)
28# Korey Sewell
29
30import os
31import sys
32import re
33import string
34import traceback
35# get type names

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1405 return '%s = bits(%s, %d, 0);\n' % \
1406 (self.base_name, base, self.size-1)
1407
1408 def makeWrite(self):
1409 if (self.ctype == 'float' or self.ctype == 'double'):
1410 error(0, 'Attempt to write control register as FP')
1411 wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
1412 (self.dest_reg_idx, self.base_name)
1413 wb += 'if (traceData) { traceData->setData(%s); }' % \
1414 self.base_name
1415 return wb
1414
1415class ControlBitfieldOperand(ControlRegOperand):
1416 def makeRead(self):
1417 bit_select = 0
1418 if (self.ctype == 'float' or self.ctype == 'double'):
1419 error(0, 'Attempt to read control register as FP')
1420 base = 'xc->readMiscReg(%s)' % self.reg_spec
1421 name = self.base_name

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1417class ControlBitfieldOperand(ControlRegOperand):
1418 def makeRead(self):
1419 bit_select = 0
1420 if (self.ctype == 'float' or self.ctype == 'double'):
1421 error(0, 'Attempt to read control register as FP')
1422 base = 'xc->readMiscReg(%s)' % self.reg_spec
1423 name = self.base_name

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