isa_parser.py (4115:cc1d6df13c7d) isa_parser.py (4185:42c0395a03f9)
1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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1363 c += '\n\t_destRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
1364 (self.dest_reg_idx, self.reg_spec)
1365 return c
1366
1367 def makeRead(self):
1368 bit_select = 0
1369 if (self.ctype == 'float' or self.ctype == 'double'):
1370 error(0, 'Attempt to read control register as FP')
1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 1354 unchanged lines hidden (view full) ---

1363 c += '\n\t_destRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
1364 (self.dest_reg_idx, self.reg_spec)
1365 return c
1366
1367 def makeRead(self):
1368 bit_select = 0
1369 if (self.ctype == 'float' or self.ctype == 'double'):
1370 error(0, 'Attempt to read control register as FP')
1371 base = 'xc->readMiscRegOperandWithEffect(this, %s)' % self.src_reg_idx
1371 base = 'xc->readMiscRegOperand(this, %s)' % self.src_reg_idx
1372 if self.size == self.dflt_size:
1373 return '%s = %s;\n' % (self.base_name, base)
1374 else:
1375 return '%s = bits(%s, %d, 0);\n' % \
1376 (self.base_name, base, self.size-1)
1377
1378 def makeWrite(self):
1379 if (self.ctype == 'float' or self.ctype == 'double'):
1380 error(0, 'Attempt to write control register as FP')
1372 if self.size == self.dflt_size:
1373 return '%s = %s;\n' % (self.base_name, base)
1374 else:
1375 return '%s = bits(%s, %d, 0);\n' % \
1376 (self.base_name, base, self.size-1)
1377
1378 def makeWrite(self):
1379 if (self.ctype == 'float' or self.ctype == 'double'):
1380 error(0, 'Attempt to write control register as FP')
1381 wb = 'xc->setMiscRegOperandWithEffect(this, %s, %s);\n' % \
1381 wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
1382 (self.dest_reg_idx, self.base_name)
1383 wb += 'if (traceData) { traceData->setData(%s); }' % \
1384 self.base_name
1385 return wb
1386
1387class MemOperand(Operand):
1388 def isMem(self):
1389 return 1

--- 504 unchanged lines hidden --- 		1382 (self.dest_reg_idx, self.base_name)
1383 wb += 'if (traceData) { traceData->setData(%s); }' % \
1384 self.base_name
1385 return wb
1386
1387class MemOperand(Operand):
1388 def isMem(self):
1389 return 1

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