isa_parser.py (3823:1c8f87aa103e) | isa_parser.py (3829:6612f906efd5) |
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1# Copyright (c) 2003-2005 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 1166 unchanged lines hidden (view full) --- 1175 c += '\n\t_destRegIdx[%d] = %s;' % \ 1176 (self.dest_reg_idx, self.reg_spec) 1177 return c 1178 1179 def makeRead(self): 1180 if (self.ctype == 'float' or self.ctype == 'double'): 1181 error(0, 'Attempt to read integer register as FP') 1182 if (self.size == self.dflt_size): | 1# Copyright (c) 2003-2005 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 1166 unchanged lines hidden (view full) --- 1175 c += '\n\t_destRegIdx[%d] = %s;' % \ 1176 (self.dest_reg_idx, self.reg_spec) 1177 return c 1178 1179 def makeRead(self): 1180 if (self.ctype == 'float' or self.ctype == 'double'): 1181 error(0, 'Attempt to read integer register as FP') 1182 if (self.size == self.dflt_size): |
1183 return '%s = xc->readIntReg(this, %d);\n' % \ | 1183 return '%s = xc->readIntRegOperand(this, %d);\n' % \ |
1184 (self.base_name, self.src_reg_idx) 1185 elif (self.size > self.dflt_size): | 1184 (self.base_name, self.src_reg_idx) 1185 elif (self.size > self.dflt_size): |
1186 int_reg_val = 'xc->readIntReg(this, %d)' % (self.src_reg_idx) | 1186 int_reg_val = 'xc->readIntRegOperand(this, %d)' % \ 1187 (self.src_reg_idx) |
1187 if (self.is_signed): 1188 int_reg_val = 'sext<%d>(%s)' % (self.dflt_size, int_reg_val) 1189 return '%s = %s;\n' % (self.base_name, int_reg_val) 1190 else: | 1188 if (self.is_signed): 1189 int_reg_val = 'sext<%d>(%s)' % (self.dflt_size, int_reg_val) 1190 return '%s = %s;\n' % (self.base_name, int_reg_val) 1191 else: |
1191 return '%s = bits(xc->readIntReg(this, %d), %d, 0);\n' % \ | 1192 return '%s = bits(xc->readIntRegOperand(this, %d), %d, 0);\n' % \ |
1192 (self.base_name, self.src_reg_idx, self.size-1) 1193 1194 def makeWrite(self): 1195 if (self.ctype == 'float' or self.ctype == 'double'): 1196 error(0, 'Attempt to write integer register as FP') 1197 if (self.size != self.dflt_size and self.is_signed): 1198 final_val = 'sext<%d>(%s)' % (self.size, self.base_name) 1199 else: 1200 final_val = self.base_name 1201 wb = ''' 1202 { 1203 %s final_val = %s; | 1193 (self.base_name, self.src_reg_idx, self.size-1) 1194 1195 def makeWrite(self): 1196 if (self.ctype == 'float' or self.ctype == 'double'): 1197 error(0, 'Attempt to write integer register as FP') 1198 if (self.size != self.dflt_size and self.is_signed): 1199 final_val = 'sext<%d>(%s)' % (self.size, self.base_name) 1200 else: 1201 final_val = self.base_name 1202 wb = ''' 1203 { 1204 %s final_val = %s; |
1204 xc->setIntReg(this, %d, final_val);\n | 1205 xc->setIntRegOperand(this, %d, final_val);\n |
1205 if (traceData) { traceData->setData(final_val); } 1206 }''' % (self.dflt_ctype, final_val, self.dest_reg_idx) 1207 return wb 1208 1209class FloatRegOperand(Operand): 1210 def isReg(self): 1211 return 1 1212 --- 9 unchanged lines hidden (view full) --- 1222 c += '\n\t_destRegIdx[%d] = %s + FP_Base_DepTag;' % \ 1223 (self.dest_reg_idx, self.reg_spec) 1224 return c 1225 1226 def makeRead(self): 1227 bit_select = 0 1228 width = 0; 1229 if (self.ctype == 'float'): | 1206 if (traceData) { traceData->setData(final_val); } 1207 }''' % (self.dflt_ctype, final_val, self.dest_reg_idx) 1208 return wb 1209 1210class FloatRegOperand(Operand): 1211 def isReg(self): 1212 return 1 1213 --- 9 unchanged lines hidden (view full) --- 1223 c += '\n\t_destRegIdx[%d] = %s + FP_Base_DepTag;' % \ 1224 (self.dest_reg_idx, self.reg_spec) 1225 return c 1226 1227 def makeRead(self): 1228 bit_select = 0 1229 width = 0; 1230 if (self.ctype == 'float'): |
1230 func = 'readFloatReg' | 1231 func = 'readFloatRegOperand' |
1231 width = 32; 1232 elif (self.ctype == 'double'): | 1232 width = 32; 1233 elif (self.ctype == 'double'): |
1233 func = 'readFloatReg' | 1234 func = 'readFloatRegOperand' |
1234 width = 64; 1235 else: | 1235 width = 64; 1236 else: |
1236 func = 'readFloatRegBits' | 1237 func = 'readFloatRegOperandBits' |
1237 if (self.ctype == 'uint32_t'): 1238 width = 32; 1239 elif (self.ctype == 'uint64_t'): 1240 width = 64; 1241 if (self.size != self.dflt_size): 1242 bit_select = 1 1243 if width: 1244 base = 'xc->%s(this, %d, %d)' % \ --- 9 unchanged lines hidden (view full) --- 1254 1255 def makeWrite(self): 1256 final_val = self.base_name 1257 final_ctype = self.ctype 1258 widthSpecifier = '' 1259 width = 0 1260 if (self.ctype == 'float'): 1261 width = 32 | 1238 if (self.ctype == 'uint32_t'): 1239 width = 32; 1240 elif (self.ctype == 'uint64_t'): 1241 width = 64; 1242 if (self.size != self.dflt_size): 1243 bit_select = 1 1244 if width: 1245 base = 'xc->%s(this, %d, %d)' % \ --- 9 unchanged lines hidden (view full) --- 1255 1256 def makeWrite(self): 1257 final_val = self.base_name 1258 final_ctype = self.ctype 1259 widthSpecifier = '' 1260 width = 0 1261 if (self.ctype == 'float'): 1262 width = 32 |
1262 func = 'setFloatReg' | 1263 func = 'setFloatRegOperand' |
1263 elif (self.ctype == 'double'): 1264 width = 64 | 1264 elif (self.ctype == 'double'): 1265 width = 64 |
1265 func = 'setFloatReg' | 1266 func = 'setFloatRegOperand' |
1266 elif (self.ctype == 'uint32_t'): | 1267 elif (self.ctype == 'uint32_t'): |
1267 func = 'setFloatRegBits' | 1268 func = 'setFloatRegOperandBits' |
1268 width = 32 1269 elif (self.ctype == 'uint64_t'): | 1269 width = 32 1270 elif (self.ctype == 'uint64_t'): |
1270 func = 'setFloatRegBits' | 1271 func = 'setFloatRegOperandBits' |
1271 width = 64 1272 else: | 1272 width = 64 1273 else: |
1273 func = 'setFloatRegBits' | 1274 func = 'setFloatRegOperandBits' |
1274 final_ctype = 'uint%d_t' % self.dflt_size 1275 if (self.size != self.dflt_size and self.is_signed): 1276 final_val = 'sext<%d>(%s)' % (self.size, self.base_name) 1277 if width: 1278 widthSpecifier = ', %d' % width 1279 wb = ''' 1280 { 1281 %s final_val = %s; --- 547 unchanged lines hidden --- | 1275 final_ctype = 'uint%d_t' % self.dflt_size 1276 if (self.size != self.dflt_size and self.is_signed): 1277 final_val = 'sext<%d>(%s)' % (self.size, self.base_name) 1278 if width: 1279 widthSpecifier = ', %d' % width 1280 wb = ''' 1281 { 1282 %s final_val = %s; --- 547 unchanged lines hidden --- |