| isa_parser.py (3274:75d7e0bc4c1b) | isa_parser.py (3419:8d92cb467ce4) |
|---|---|
| 1# Copyright (c) 2003-2005 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 1302 unchanged lines hidden (view full) --- 1311 return '%s = %s;\n' % (self.base_name, base) 1312 else: 1313 return '%s = bits(%s, %d, 0);\n' % \ 1314 (self.base_name, base, self.size-1) 1315 1316 def makeWrite(self): 1317 if (self.ctype == 'float' or self.ctype == 'double'): 1318 error(0, 'Attempt to write control register as FP') | 1# Copyright (c) 2003-2005 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 1302 unchanged lines hidden (view full) --- 1311 return '%s = %s;\n' % (self.base_name, base) 1312 else: 1313 return '%s = bits(%s, %d, 0);\n' % \ 1314 (self.base_name, base, self.size-1) 1315 1316 def makeWrite(self): 1317 if (self.ctype == 'float' or self.ctype == 'double'): 1318 error(0, 'Attempt to write control register as FP') |
| 1319 wb = 'xc->setMiscReg(%s, %s);\n' % (self.reg_spec, self.base_name) | 1319 wb = 'xc->setMiscRegWithEffect(%s, %s);\n' % (self.reg_spec, self.base_name) |
| 1320 wb += 'if (traceData) { traceData->setData(%s); }' % \ 1321 self.base_name 1322 return wb 1323 1324class MemOperand(Operand): 1325 def isMem(self): 1326 return 1 1327 --- 501 unchanged lines hidden --- | 1320 wb += 'if (traceData) { traceData->setData(%s); }' % \ 1321 self.base_name 1322 return wb 1323 1324class MemOperand(Operand): 1325 def isMem(self): 1326 return 1 1327 --- 501 unchanged lines hidden --- |