isa_parser.py (10934:5af8f40d8f2c) isa_parser.py (10935:acd48ddd725f)
1# Copyright (c) 2014 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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510 return 0
511
512 def isIntReg(self):
513 return 0
514
515 def isCCReg(self):
516 return 0
517
1# Copyright (c) 2014 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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510 return 0
511
512 def isIntReg(self):
513 return 0
514
515 def isCCReg(self):
516 return 0
517
518 def isVectorReg(self):
519 return 0
520
521 def isControlReg(self):
522 return 0
523
524 def isPCState(self):
525 return 0
526
527 def isPCPart(self):
528 return self.isPCState() and self.reg_spec

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749 {
750 %s final_val = %s;
751 xc->setCCRegOperand(this, %s, final_val);\n
752 if (traceData) { traceData->setData(final_val); }
753 }''' % (wcond, self.ctype, self.base_name, windex)
754
755 return wb
756
518 def isControlReg(self):
519 return 0
520
521 def isPCState(self):
522 return 0
523
524 def isPCPart(self):
525 return self.isPCState() and self.reg_spec

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746 {
747 %s final_val = %s;
748 xc->setCCRegOperand(this, %s, final_val);\n
749 if (traceData) { traceData->setData(final_val); }
750 }''' % (wcond, self.ctype, self.base_name, windex)
751
752 return wb
753
757class VectorRegOperand(Operand):
758 def isReg(self):
759 return 1
760
761 def isVectorReg(self):
762 return 1
763
764 def __init__(self, parser, full_name, ext, is_src, is_dest):
765 ## Vector registers are always treated as source registers since
766 ## not the whole of them might be written, in which case we need
767 ## to retain the earlier value.
768 super(VectorRegOperand, self).__init__(parser, full_name, ext,
769 True, is_dest)
770 self.size = 0
771
772 def finalize(self, predRead, predWrite):
773 self.flags = self.getFlags()
774 self.constructor = self.makeConstructor(predRead, predWrite)
775 self.op_decl = self.makeDecl()
776
777 if self.is_src:
778 self.op_rd = self.makeRead(predRead)
779 self.op_src_decl = self.makeDecl()
780 else:
781 self.op_rd = ''
782 self.op_src_decl = ''
783
784 if self.is_dest:
785 self.op_wb = self.makeWrite(predWrite)
786 self.op_dest_decl = self.makeDecl()
787 else:
788 self.op_wb = ''
789 self.op_dest_decl = ''
790
791 def makeConstructor(self, predRead, predWrite):
792 c_src = ''
793 c_dest = ''
794
795 if self.is_src:
796 c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + Vector_Reg_Base;' % \
797 (self.reg_spec)
798 if self.hasReadPred():
799 c_src = '\n\tif (%s) {%s\n\t}' % \
800 (self.read_predicate, c_src)
801
802 if self.is_dest:
803 c_dest = '\n\t_destRegIdx[_numDestRegs++] = %s + Vector_Reg_Base;' % \
804 (self.reg_spec)
805 c_dest += '\n\t_numVectorDestRegs++;'
806 if self.hasWritePred():
807 c_dest = '\n\tif (%s) {%s\n\t}' % \
808 (self.write_predicate, c_dest)
809
810 return c_src + c_dest
811
812 def makeRead(self, predRead):
813 if self.read_code != None:
814 return self.buildReadCode('readVectorRegOperand')
815
816 vector_reg_val = ''
817 if predRead:
818 vector_reg_val = 'xc->readVectorRegOperand(this, _sourceIndex++)'
819 if self.hasReadPred():
820 vector_reg_val = '(%s) ? %s : 0' % \
821 (self.read_predicate, vector_reg_val)
822 else:
823 vector_reg_val = 'xc->readVectorRegOperand(this, %d)' % \
824 self.src_reg_idx
825
826 return '%s = %s;\n' % (self.base_name, vector_reg_val)
827
828 def makeWrite(self, predWrite):
829 if self.write_code != None:
830 return self.buildWriteCode('setVectorRegOperand')
831
832 if predWrite:
833 wp = 'true'
834 if self.hasWritePred():
835 wp = self.write_predicate
836
837 wcond = 'if (%s)' % (wp)
838 windex = '_destIndex++'
839 else:
840 wcond = ''
841 windex = '%d' % self.dest_reg_idx
842
843 wb = '''
844 %s
845 {
846 TheISA::VectorReg final_val = %s;
847 xc->setVectorRegOperand(this, %s, final_val);\n
848 if (traceData) { traceData->setData(final_val); }
849 }''' % (wcond, self.base_name, windex)
850
851 return wb
852
853 def makeDecl(self):
854 ctype = 'TheISA::VectorReg'
855 return '%s %s;\n' % (ctype, self.base_name)
856
857class ControlRegOperand(Operand):
858 def isReg(self):
859 return 1
860
861 def isControlReg(self):
862 return 1
863
864 def makeConstructor(self, predRead, predWrite):

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916
917 def makeConstructor(self, predRead, predWrite):
918 return ''
919
920 def makeDecl(self):
921 # Note that initializations in the declarations are solely
922 # to avoid 'uninitialized variable' errors from the compiler.
923 # Declare memory data variable.
754class ControlRegOperand(Operand):
755 def isReg(self):
756 return 1
757
758 def isControlReg(self):
759 return 1
760
761 def makeConstructor(self, predRead, predWrite):

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813
814 def makeConstructor(self, predRead, predWrite):
815 return ''
816
817 def makeDecl(self):
818 # Note that initializations in the declarations are solely
819 # to avoid 'uninitialized variable' errors from the compiler.
820 # Declare memory data variable.
924 if 'IsVector' in self.flags:
925 return 'TheISA::VectorReg %s;\n' % self.base_name
926 else:
927 return '%s %s = 0;\n' % (self.ctype, self.base_name)
821 return '%s %s = 0;\n' % (self.ctype, self.base_name)
928
929 def makeRead(self, predRead):
930 if self.read_code != None:
931 return self.buildReadCode()
932 return ''
933
934 def makeWrite(self, predWrite):
935 if self.write_code != None:

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1010 self.sort()
1011 # enumerate source & dest register operands... used in building
1012 # constructor later
1013 self.numSrcRegs = 0
1014 self.numDestRegs = 0
1015 self.numFPDestRegs = 0
1016 self.numIntDestRegs = 0
1017 self.numCCDestRegs = 0
822
823 def makeRead(self, predRead):
824 if self.read_code != None:
825 return self.buildReadCode()
826 return ''
827
828 def makeWrite(self, predWrite):
829 if self.write_code != None:

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904 self.sort()
905 # enumerate source & dest register operands... used in building
906 # constructor later
907 self.numSrcRegs = 0
908 self.numDestRegs = 0
909 self.numFPDestRegs = 0
910 self.numIntDestRegs = 0
911 self.numCCDestRegs = 0
1018 self.numVectorDestRegs = 0
1019 self.numMiscDestRegs = 0
1020 self.memOperand = None
1021
1022 # Flags to keep track if one or more operands are to be read/written
1023 # conditionally.
1024 self.predRead = False
1025 self.predWrite = False
1026

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1033 op_desc.dest_reg_idx = self.numDestRegs
1034 self.numDestRegs += 1
1035 if op_desc.isFloatReg():
1036 self.numFPDestRegs += 1
1037 elif op_desc.isIntReg():
1038 self.numIntDestRegs += 1
1039 elif op_desc.isCCReg():
1040 self.numCCDestRegs += 1
912 self.numMiscDestRegs = 0
913 self.memOperand = None
914
915 # Flags to keep track if one or more operands are to be read/written
916 # conditionally.
917 self.predRead = False
918 self.predWrite = False
919

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926 op_desc.dest_reg_idx = self.numDestRegs
927 self.numDestRegs += 1
928 if op_desc.isFloatReg():
929 self.numFPDestRegs += 1
930 elif op_desc.isIntReg():
931 self.numIntDestRegs += 1
932 elif op_desc.isCCReg():
933 self.numCCDestRegs += 1
1041 elif op_desc.isVectorReg():
1042 self.numVectorDestRegs += 1
1043 elif op_desc.isControlReg():
1044 self.numMiscDestRegs += 1
1045 elif op_desc.isMem():
1046 if self.memOperand:
1047 error("Code block has more than one memory operand.")
1048 self.memOperand = op_desc
1049
1050 # Check if this operand has read/write predication. If true, then

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1231 # The header of the constructor declares the variables to be used
1232 # in the body of the constructor.
1233 header = ''
1234 header += '\n\t_numSrcRegs = 0;'
1235 header += '\n\t_numDestRegs = 0;'
1236 header += '\n\t_numFPDestRegs = 0;'
1237 header += '\n\t_numIntDestRegs = 0;'
1238 header += '\n\t_numCCDestRegs = 0;'
934 elif op_desc.isControlReg():
935 self.numMiscDestRegs += 1
936 elif op_desc.isMem():
937 if self.memOperand:
938 error("Code block has more than one memory operand.")
939 self.memOperand = op_desc
940
941 # Check if this operand has read/write predication. If true, then

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1122 # The header of the constructor declares the variables to be used
1123 # in the body of the constructor.
1124 header = ''
1125 header += '\n\t_numSrcRegs = 0;'
1126 header += '\n\t_numDestRegs = 0;'
1127 header += '\n\t_numFPDestRegs = 0;'
1128 header += '\n\t_numIntDestRegs = 0;'
1129 header += '\n\t_numCCDestRegs = 0;'
1239 header += '\n\t_numVectorDestRegs = 0;'
1240
1241 self.constructor = header + \
1242 self.operands.concatAttrStrings('constructor')
1243
1244 self.flags = self.operands.concatAttrLists('flags')
1245
1246 self.op_class = None
1247

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2397 self.operandNameMap = operand_name
2398
2399 # Define operand variables.
2400 operands = user_dict.keys()
2401 extensions = self.operandTypeMap.keys()
2402
2403 operandsREString = r'''
2404 (?<!\w) # neg. lookbehind assertion: prevent partial matches
1130
1131 self.constructor = header + \
1132 self.operands.concatAttrStrings('constructor')
1133
1134 self.flags = self.operands.concatAttrLists('flags')
1135
1136 self.op_class = None
1137

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2287 self.operandNameMap = operand_name
2288
2289 # Define operand variables.
2290 operands = user_dict.keys()
2291 extensions = self.operandTypeMap.keys()
2292
2293 operandsREString = r'''
2294 (?<!\w) # neg. lookbehind assertion: prevent partial matches
2405 ((%s)(?:_(%s))?(?:\[\w+\])?) # match: operand with optional '_'
2406 # then suffix, and then an optional array index.
2295 ((%s)(?:_(%s))?) # match: operand with optional '_' then suffix
2407 (?!\w) # neg. lookahead assertion: prevent partial matches
2408 ''' % (string.join(operands, '|'), string.join(extensions, '|'))
2409
2410 self.operandsRE = re.compile(operandsREString, re.MULTILINE|re.VERBOSE)
2411
2412 # Same as operandsREString, but extension is mandatory, and only two
2413 # groups are returned (base and ext, not full name as above).
2414 # Used for subtituting '_' for '.' to make C++ identifiers.

--- 113 unchanged lines hidden --- 		2296 (?!\w) # neg. lookahead assertion: prevent partial matches
2297 ''' % (string.join(operands, '|'), string.join(extensions, '|'))
2298
2299 self.operandsRE = re.compile(operandsREString, re.MULTILINE|re.VERBOSE)
2300
2301 # Same as operandsREString, but extension is mandatory, and only two
2302 # groups are returned (base and ext, not full name as above).
2303 # Used for subtituting '_' for '.' to make C++ identifiers.

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