1# Copyright (c) 2003-2005 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 1253 unchanged lines hidden (view full) --- 1262 return 0 1263 1264 def isIntReg(self): 1265 return 0 1266 1267 def isControlReg(self): 1268 return 0 1269 |
1270 def getFlags(self): 1271 # note the empty slice '[:]' gives us a copy of self.flags[0] 1272 # instead of a reference to it 1273 my_flags = self.flags[0][:] 1274 if self.is_src: 1275 my_flags += self.flags[1] 1276 if self.is_dest: 1277 my_flags += self.flags[2] --- 148 unchanged lines hidden (view full) --- 1426 if self.write_code != None: 1427 return self.buildWriteCode('setMiscRegOperand') 1428 wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \ 1429 (self.dest_reg_idx, self.base_name) 1430 wb += 'if (traceData) { traceData->setData(%s); }' % \ 1431 self.base_name 1432 return wb 1433 |
1434class ControlBitfieldOperand(ControlRegOperand): 1435 def makeRead(self): 1436 bit_select = 0 1437 if (self.ctype == 'float' or self.ctype == 'double'): 1438 error(0, 'Attempt to read control register as FP') 1439 if self.read_code != None: 1440 return self.buildReadCode('readMiscReg') 1441 base = 'xc->readMiscReg(%s)' % self.reg_spec --- 613 unchanged lines hidden --- |