1# Copyright (c) 2014, 2016, 2019 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 476 unchanged lines hidden (view full) --- 485 return 0 486 487 def isVecReg(self): 488 return 0 489 490 def isVecElem(self): 491 return 0 492 |
493 def isVecPredReg(self): 494 return 0 495 |
496 def isPCState(self): 497 return 0 498 499 def isPCPart(self): 500 return self.isPCState() and self.reg_spec 501 502 def hasReadPred(self): 503 return self.read_predicate != None --- 289 unchanged lines hidden (view full) --- 793 794 def makeWrite(self, predWrite): 795 func = 'setVecRegOperand' 796 if self.write_code != None: 797 return self.buildWriteCode(func) 798 799 wb = ''' 800 if (traceData) { |
801 traceData->setData(tmp_d%d); |
802 } |
803 ''' % self.dest_reg_idx |
804 return wb 805 806 def finalize(self, predRead, predWrite): 807 super(VecRegOperand, self).finalize(predRead, predWrite) 808 if self.is_dest: 809 self.op_rd = self.makeReadW(predWrite) + self.op_rd 810 811class VecElemOperand(Operand): --- 45 unchanged lines hidden (view full) --- 857 else: 858 c_write = self.base_name 859 860 c_write = ('\n\txc->setVecElemOperand(this, %d, %s);' % 861 (self.dest_reg_idx, c_write)) 862 863 return c_write 864 |
865class VecPredRegOperand(Operand): 866 reg_class = 'VecPredRegClass' 867 868 def __init__(self, parser, full_name, ext, is_src, is_dest): 869 Operand.__init__(self, parser, full_name, ext, is_src, is_dest) 870 self.parser = parser 871 872 def isReg(self): 873 return 1 874 875 def isVecPredReg(self): 876 return 1 877 878 def makeDecl(self): 879 return '' 880 881 def makeConstructor(self, predRead, predWrite): 882 c_src = '' 883 c_dest = '' 884 885 if self.is_src: 886 c_src = src_reg_constructor % (self.reg_class, self.reg_spec) 887 888 if self.is_dest: 889 c_dest = dst_reg_constructor % (self.reg_class, self.reg_spec) 890 c_dest += '\n\t_numVecPredDestRegs++;' 891 892 return c_src + c_dest 893 894 def makeRead(self, predRead): 895 func = 'readVecPredRegOperand' 896 if self.read_code != None: 897 return self.buildReadCode(func) 898 899 if predRead: 900 rindex = '_sourceIndex++' 901 else: 902 rindex = '%d' % self.src_reg_idx 903 904 c_read = '\t\t%s& tmp_s%s = xc->%s(this, %s);\n' % ( 905 'const TheISA::VecPredRegContainer', rindex, func, rindex) 906 if self.ext: 907 c_read += '\t\tauto %s = tmp_s%s.as<%s>();\n' % ( 908 self.base_name, rindex, 909 self.parser.operandTypeMap[self.ext]) 910 return c_read 911 912 def makeReadW(self, predWrite): 913 func = 'getWritableVecPredRegOperand' 914 if self.read_code != None: 915 return self.buildReadCode(func) 916 917 if predWrite: 918 rindex = '_destIndex++' 919 else: 920 rindex = '%d' % self.dest_reg_idx 921 922 c_readw = '\t\t%s& tmp_d%s = xc->%s(this, %s);\n' % ( 923 'TheISA::VecPredRegContainer', rindex, func, rindex) 924 if self.ext: 925 c_readw += '\t\tauto %s = tmp_d%s.as<%s>();\n' % ( 926 self.base_name, rindex, 927 self.parser.operandTypeMap[self.ext]) 928 return c_readw 929 930 def makeWrite(self, predWrite): 931 func = 'setVecPredRegOperand' 932 if self.write_code != None: 933 return self.buildWriteCode(func) 934 935 wb = ''' 936 if (traceData) { 937 traceData->setData(tmp_d%d); 938 } 939 ''' % self.dest_reg_idx 940 return wb 941 942 def finalize(self, predRead, predWrite): 943 super(VecPredRegOperand, self).finalize(predRead, predWrite) 944 if self.is_dest: 945 self.op_rd = self.makeReadW(predWrite) + self.op_rd 946 |
947class CCRegOperand(Operand): 948 reg_class = 'CCRegClass' 949 950 def isReg(self): 951 return 1 952 953 def isCCReg(self): 954 return 1 --- 237 unchanged lines hidden (view full) --- 1192 self.sort() 1193 # enumerate source & dest register operands... used in building 1194 # constructor later 1195 self.numSrcRegs = 0 1196 self.numDestRegs = 0 1197 self.numFPDestRegs = 0 1198 self.numIntDestRegs = 0 1199 self.numVecDestRegs = 0 |
1200 self.numVecPredDestRegs = 0 |
1201 self.numCCDestRegs = 0 1202 self.numMiscDestRegs = 0 1203 self.memOperand = None 1204 1205 # Flags to keep track if one or more operands are to be read/written 1206 # conditionally. 1207 self.predRead = False 1208 self.predWrite = False --- 7 unchanged lines hidden (view full) --- 1216 op_desc.dest_reg_idx = self.numDestRegs 1217 self.numDestRegs += 1 1218 if op_desc.isFloatReg(): 1219 self.numFPDestRegs += 1 1220 elif op_desc.isIntReg(): 1221 self.numIntDestRegs += 1 1222 elif op_desc.isVecReg(): 1223 self.numVecDestRegs += 1 |
1224 elif op_desc.isVecPredReg(): 1225 self.numVecPredDestRegs += 1 |
1226 elif op_desc.isCCReg(): 1227 self.numCCDestRegs += 1 1228 elif op_desc.isControlReg(): 1229 self.numMiscDestRegs += 1 1230 elif op_desc.isMem(): 1231 if self.memOperand: 1232 error("Code block has more than one memory operand.") 1233 self.memOperand = op_desc --- 192 unchanged lines hidden (view full) --- 1426 # The header of the constructor declares the variables to be used 1427 # in the body of the constructor. 1428 header = '' 1429 header += '\n\t_numSrcRegs = 0;' 1430 header += '\n\t_numDestRegs = 0;' 1431 header += '\n\t_numFPDestRegs = 0;' 1432 header += '\n\t_numVecDestRegs = 0;' 1433 header += '\n\t_numVecElemDestRegs = 0;' |
1434 header += '\n\t_numVecPredDestRegs = 0;' |
1435 header += '\n\t_numIntDestRegs = 0;' 1436 header += '\n\t_numCCDestRegs = 0;' 1437 1438 self.constructor = header + \ 1439 self.operands.concatAttrStrings('constructor') 1440 1441 self.flags = self.operands.concatAttrLists('flags') 1442 --- 1277 unchanged lines hidden --- |